Balanced negative bitline voltage for a write assist circuit

A device comprising:

• a first transistor switch connected to a near-end of a bitline and a second transistor switch connected to a far-end of a bitline, the first and second transistor switches responsive to a pass signal;
• a MOS capacitor and a metal capacitor connected in parallel, the MOS capacitor connected directly to at least one of the first transistor switch and the second transistor switch and the metal capacitor being directly connected to both the first and second transistor switches;
• and
• a control circuit, the control circuit providing a kick signal during a write operation, the kick signal falling from a ground level to a negative level, wherein application of the kick signal to the MOS capacitor and the metal capacitor creates a balanced coupling between the kick signal voltage and the voltage at the near-end and the far-end during the time that the pass signal is applied to the first and second switch transistors.

A method of establishing a balanced negative voltage to a near-end and far-end of a bitline, comprising:

• connecting a MOS capacitor and a metal capacitor in parallel, with a second plate of the MOS capacitor connected to a near-end of a bitline through a first switch transistor and a second plate of the metal capacitor connected to the near-end of the bitline through the first switch transistor and a far end of the bitline through a second switch transistor;
• applying a falling negative kick voltage to the first plates of the MOS capacitor and the metal capacitor;
• and
• turning on the first and second switch transistors, wherein the MOS capacitor and the metal capacitor are coupled to the voltage at the near-end and far-end and provide a balanced voltage to the bitline approximately equal to the kick voltage for a period of time.