Power supply generator assist
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYen-An Chang, Po-Hao Lee, Yi-Chun Shih
Life of this patent
Estimating the term…
Abstract
The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.
Claims20
A system, comprising:
- a voltage assist circuit configured to selectively supply an assist voltage signal to a power supply generator in response to a load, wherein the voltage assist circuit includes:
- a charge pump,
- a driver circuit receiving a control signal from the charge pump;
- a first control circuit configured to control the voltage assist circuit in response to the control signal from the charge pump;
- and
- a second control circuit configured to control the voltage assist circuit in response to the assist voltage signal.
A method comprising:
- providing a voltage signal from a power supply to a load;
- selectively providing a voltage assist signal to inject a current into the load, including:
- outputting a control signal to an assist driver circuit from a charge pump, wherein the assist driver circuit is configured to output the voltage assist signal;
- outputting a first enable signal to the charge pump in response to the first voltage assist signal level being less than a reference voltage, to regulate the control signal at a first level to turn on the assist driver circuit and inject the current to the load;
- and
- outputting a second enable signal to the charge pump in response to the second control signal level being less than the reference voltage, to regulate the control signal at a second level to maintain the control signal at a predetermined voltage level.
A system comprising:
- a memory cell;
- a power supply generator circuit configured to produce a bit line voltage for the memory cell;
- a voltage assist circuit, connected to an output of the power supply generator circuit,
- wherein the voltage assist circuit includes:
- a driver circuit configured to inject a drive current to an output of the voltage assist circuit when enabled;
- a charge pump circuit connected to the input of the driver circuit and configured to control the operation of the driver circuit;
- an active level detector circuit connected to the output of the driver circuit and configured to detect the bit line voltage;
- a standby level detector circuit connected to an input of the driver circuit;
- a control logic circuit, wherein outputs of the active level detector circuit and the standby level detector circuit are connected to inputs of the control logic circuit and an output of the control logic circuit is connected to an input of the charge pump circuit;
- wherein, upon detecting that the memory cell is performing a write operation and in need of a current injection, the active level detector circuit is configured to produce a first output enable signal that controls the operation of the charge pump circuit in order to boost the output of the charge pump circuit to a target level;
- wherein, upon detecting that the memory cell is in a standby mode, the standby level detector circuit is configured to produce a second output enable signal that regulates the operation of the charge pump circuit such that the output of the charge pump circuit remains at the target level during the standby mode;
- and
- wherein the target level is the sum of the bit line voltage of the memory cell and a threshold voltage of the driver circuit.
Dependencies are inferred from the claim text.