Reducing read disturbance error in tag array

A tag array of a cache memory, the tag array comprising:

• a plurality of bit lines comprising a plurality of lower bit lines and a plurality of higher bit lines;
• a plurality of tag ways, a kth tag way of the plurality of tag ways where 0≤k≤K−1 and K is a number of the plurality of tag ways comprising a kth plurality of sets, each respective set of the kth plurality of sets comprising a respective plurality of memory cells, comprising:
• a respective plurality of lower memory cells, each respective lower memory cell of the respective plurality of lower memory cells comprising:
• a respective lower storage element coupled to a respective lower bit line of the plurality of lower bit lines and configured to store a respective Least Significant Bit (LSB) of a respective plurality of LSBs;
• and
• a respective lower access transistor connected to the respective lower storage element and configured to load data stored in the respective lower storage element to the respective lower bit line responsive to the respective lower access transistor being activated;
• a respective plurality of higher memory cells, each respective higher memory cell of a respective plurality of higher memory cells comprising:
• a respective higher storage element coupled to a respective higher bit line of the plurality of higher bit lines and configured to store a respective Most Significant Bit (MSB) of a respective plurality of MSBs;
• and
• a respective higher access transistor connected to the respective higher storage element and configured to load data stored in the respective higher storage element to the respective higher bit line responsive to the respective higher access transistor being activated;
• a decoder coupled to the plurality of tag ways, the decoder configured to enable access to an (i, k)th set of the kth plurality of sets based on a value of an index of a requested address in the cache memory, where 0≤i≤h−1 and h is a number of the kth plurality of sets;
• a plurality of m-bit comparators where m is a number of an (i, k)th plurality of LSBs of the (i, k)th set, a kth m-bit comparator of the plurality of m-bit comparators configured to:
• access the (i, k)th plurality of LSBs responsive to the access to the (i, k)th set being enabled by the decoder;
• compare the (i, k)th plurality of LSBs with m lower bits of a tag of the requested address;
• and
• enable access to an (i, k)th plurality of MSBs of the (i, k)th set responsive to each respective LSB of the (i, k)th plurality of LSBs being equal to a respective lower bit of the tag;
• a plurality of n-bit comparators where n is a number of the (i, k)th plurality of MSBs, a kthn-bit comparator of the plurality of n-bit comparators configured to:
• access the (i, k)th plurality of MSBs responsive to the access to the (i, k)th plurality of MSBs being enabled by the kth m-bit comparator;
• compare the (i, k)th plurality of MSBs with n higher bits of the tag;
• and
• enable access to the (i, k)th set responsive to each respective MSB of the (i, k)th plurality of MSBs being equal to a respective higher bit of the tag;
• a data bus configured to access the (i, k)th set responsive to the access to the (i, k)th set being enabled by the kthn-bit comparator;
• a plurality of latch circuits, a kth latch circuit of the plurality of latch circuits configured to:
• enable access of the decoder to the (i, k)th plurality of LSBs responsive to receiving a request signal associated with a read operation from the cache memory;
• and
• disable access of the decoder to the (i, k)th plurality of LSBs responsive the decoder accessing the (i, k)th plurality of LSBs;
• a plurality of LSB transition gates, an (i, k)th LSB transition gate of the plurality of LSB transition gates configured to enable access of the decoder to the (i, k)th plurality of LSBs responsive to the (i, k)th LSB transition gate being activated by the kth latch circuit;
• a plurality of MSB transition gates, an (i, k)th MSB transition gate of the plurality of MSB transition gates configured to enable access of the decoder to the (i, k)th plurality of MSBs responsive to the (i, k)th MSB transition gate being activated by the kth m-bit comparator;
• an m-bit sense amplifier coupled to the plurality of lower bit lines, the m-bit sense amplifier configured to amplify signals on each of the plurality of lower bit lines;
• and
• a plurality of buffer circuits, a kth buffer circuit of the plurality of buffer circuits configured to load data stored in the (i, k)th set on the data bus responsive to each respective MSB of the (i, k)th plurality of MSBs being equal to a respective higher bit of the tag, the kth buffer circuit comprising a buffer control input coupled to the kth n-bit comparator, buffer control input configured to activate the kth buffer circuit responsive to being activated by the kthn-bit comparator.