Integrated circuit

An integrated circuit, comprising:

• a plurality of memory cells comprising a first array of memory cells and a second array of memory cells;
• a first pair of complementary data lines coupled to the first array of memory cells;
• a second pair of complementary data lines coupled to the second array of memory cells;
• a plurality of first word lines arranged in a first segment of a memory bank, and coupled to the first array of memory cells;
• and
• a plurality of second word lines arranged in a second segment, of the memory bank, that is disposed between the first segment and a sense amplifier, and the plurality of second word lines being coupled to the second array of memory cells;
• wherein lengths of the first pair of complementary data lines are shorter than lengths of the second pair of complementary data lines;
• wherein the plurality of first word lines and the plurality of second word lines are arranged according to a predetermined ratio of a number of the plurality of first word lines to a number of the plurality of second word lines;
• wherein the predetermined ratio is less than 1.

A method, comprising:

• generating, by a decoder circuit, based on a word line address, a first control signal and a second control signal;
• activating, based on the word line address, one of a plurality of first word lines or one of a plurality of second word lines;
• and
• accessing, in response to the first control signal and the second control signal, a memory cell coupled to an activated word line of the plurality of first word lines or the plurality of second word lines;
• wherein the first control signal and the second control signal are associated with a predetermined ratio of a number of the plurality of first word lines to a number of the plurality of second word lines.