Memory device including on-die-termination circuit

A memory system comprising:

• a NAND flash memory device;
• and
• a controller configured to control the memory device,
• wherein the memory device comprises:
• a first chip enable signal pin that receives a first chip enable signal;
• a second chip enable signal pin that receives a second chip enable signal;
• a first memory chip including a first on-die-termination (ODT) circuit and a second memory chip including a second ODT circuit, wherein the first memory chip and second memory chip are commonly connected to the first chip enable signal pin;
• a third memory chip including a third ODT circuit and a fourth memory chip including a fourth ODT circuit, wherein the third memory chip and fourth memory chip are commonly connected to the second chip enable signal pin;
• and
• an ODT pin that receives an ODT signal, wherein the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are commonly connected to the ODT pin,
• wherein in response to the ODT signal, the first ODT circuit uses a first ODT resistor to terminate a signal received by at least one of the first memory chip, the second memory chip, the third memory chip and the fourth memory chip, the second ODT circuit uses a second ODT resistor to terminate the signal, the third ODT circuit uses a third ODT resistor to terminate the signal, or the fourth ODT circuit uses a fourth ODT resistor to terminate the signal.

A memory system comprising:

• a NAND flash memory device;
• and
• a controller configured to control the memory device,
• wherein the memory device comprises:
• a first memory chip and a second memory chip;
• at least one chip enable signal pin that receives at least one chip enable signal selectively enabling at least one of the first memory chip and the second memory chip;
• a first on-die-termination (ODT) pin that receives a first ODT signal activated in a write operation for one of the first memory chip and the second memory chip;
• and
• a second ODT pin configured to receive a second ODT signal activated in a read operation for one of the first memory chip and the second memory chip,
• wherein each of the first memory chip and the second memory chip comprises:
• a first ODT circuit enabled in response to the first ODT signal, such that either a first ODT resistor or a second ODT resistor is used to terminate a signal received by at least one of the first memory chip and the second memory chip;
• and
• a second ODT circuit enabled in response to the second ODT signal, such that either a first ODT resistor or a second ODT resistor is used to terminate a signal received by at least one of the first memory chip and the second memory chip.