US 2021/0201963 A1 · PAGE BUFFER AND MEMORY DEVICE INCLUDING THE SAME

Abstract

A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.

Claims14

Dependent claims

A memory device comprising:

a memory cell array including a plurality of memory cells, and a plurality of bit lines connected to the plurality of memory cells;
and
a memory controller configured to read data corresponding to a threshold voltage of a selected memory cell connected to a selected bit line among the plurality of bit lines, input a first charging current to the selected bit line during a first period of time, and input a second charging current lower than the first charging current to the selected bit line during a second period of time, after the first period of time, when the threshold voltage of the selected memory cell is higher than a reference voltage.

Dependencies are inferred from the claim text.

Facts

Application

17/200,246Filed 12 Mar 2021

Priority

KR 10-2019-006274028 May 2019

Published

1 Jul 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

G11C 7/1021
Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters: page serial bit line…
G11C 7/1039
Read-write modes for single port memories, i.e. having either a random port or a serial port: using pipelining techniques, i.e. using latches…
G11C 7/1057
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output…
G11C 7/106
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output latches

Page buffer and memory device including the same

Life of this patent

Page buffer and memory device including the same

Life of this patent

Abstract

Claims14