Image sensor driving circuit including power switch and image sensor including the same

A driver circuit of an image sensor, comprising:

• a row decoder configured to decode an address and generate an operation directing signal having an enable level during a first time directing an operation of a target row of a pixel array;
• a latch comprising:
• a target row latch configured to detect the operation directing signal of the first time and to generate an operating signal having an enable level during a second time after the first time, based on the operation directing signal of the first time;
• a power gating control circuit configured to generate a power gating signal based on the operation directing signal;
• and
• a first power switch configured to connect a power supply voltage to the target row latch during the first time and the second time based on the power gating signal;
• and
• a digital logic circuit comprising:
• a target row logic circuit configured to generate a pixel control signal corresponding to the target row based on the operating signal;
• and
• a second power switch configured to connect the power supply voltage to the target row logic circuit during the first time and the second time based on the power gating signal.

An image sensor comprising:

• a pixel array comprising a plurality of pixels;
• a driver circuit connected to rows of the pixel array through row lines, the driver circuit being configured to control a first operation and a second operation of each of the rows;
• and
• a converting circuit connected to columns of the pixel array through column lines, the converting circuit being configured to receive an image signal from the pixel array through the column lines and convert the received image signal into a digital image signal, in accordance with the first operation and the second operation of the pixel array,
• wherein the driver circuit comprises:
• a row decoder configured to decode an address directing a target row of the pixel array, at which the first operation and the second operation are performed, and generate an operation directing signal corresponding to the target row;
• a digital logic circuit comprising:
• a target row logic circuit configured to generate a pixel control signal corresponding to the target row based on the operation directing signal;
• and
• a power switch configured to connect a power supply voltage to the target row logic circuit based on the operation directing signal while the target row logic circuit generates the pixel control signal corresponding to the first operation and the second operation;
• and
• a row driver configured to control the first operation and the second operation of the target row, based on the pixel control signal.