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US 2021/0201832 A1Published application
Gate driving circuit and display device using the same
AssigneeLG Display Co., Ltd.
InventorsSanghyun LIM, Nakwoo KIM, Donghyang LEE
Life of this patent
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Abstract
A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.
Claims17
A gate driving circuit comprising:
- a Q node controller generating a voltage of a Q node in accordance with a first clock, a second clock, a third clock, and a start signal;
- a QB node controller generating a voltage of a QB node in accordance with the second clock and the third clock;
- and
- an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node;
- wherein the second clock is delayed by one horizontal period from the first clock, and the third clock is delayed by one horizontal period from the second clock, and the first, second and third clocks have a cycle of three horizontal periods, a gate-on voltage interval is longer than a gate-off voltage interval and shorter than two horizontal periods, and
- wherein the start signal includes a second pulse interval synchronized with a part of the third clock.
3 more elements
A display device comprising:
- a display panel provided with a plurality of pixels disposed thereon and connected to data lines and gate lines, and one of the data lines and one of the gate lines;
- a data driving circuit for supplying a data voltage to the pixels through the data line;
- a gate driving circuit for sequentially supplying scan signals to the pixels through the gate line by including a plurality of stages connected dependently, but supplying two partially overlapping scan signals to two adjacent display lines;
- and
- a timing controller for controlling the data driving circuit and the gate driving circuit so as to display image data through the display panel,
- wherein the plurality of stages comprises:
- a Q node controller generating a voltage of a Q node in accordance with a first clock, a second clock, a third clock and a start signal;
- a QB node controller generating a voltage of a QB node in accordance with the second clock and the third clock;
- an output part including a pull-up TFT and a pull-down TFT and generating a scan signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node;
- and
- wherein the second clock is delayed by one horizontal period from the first clock, and the third clock is delayed by one horizontal period from the second clock, and the first, second and third clocks have a cycle of three horizontal periods, a gate-on voltage interval is longer than a gate-off voltage interval and shorter than two horizontal periods, and
- wherein the start signal includes a second pulse interval synchronized with a part of the third clock.
9 more elements
Dependencies are inferred from the claim text.