Shift register unit, gate driving circuit, display device and driving method

A gate driving circuit, comprising a plurality of shift register units which are cascaded, wherein the shift register unit comprises a first input circuit, an output circuit, a first control circuit, a first reset circuit, a second input circuit, a transmission circuit, and a storage circuit;

• the first input circuit is configured to control a level of a first node in response to a first input signal,
• the output circuit is configured to provide an output signal at an output terminal under control of the level of the first node,
• the first control circuit is configured to control a level of a second node under control of the level of the first node,
• the first reset circuit is configured to reset the first node and the output terminal under control of the level of the second node,
• the second input circuit is configured to control a level of a third node in response to a selection control signal,
• the transmission circuit is configured to control the level of the first node according to the level of the third node, and
• the storage circuit is electrically connected to the second node, and is configured to stabilize the level of the second node.

A method of driving a shift register unit,

• wherein the shift register unit comprises a first input circuit, an output circuit, a first control circuit, a first reset circuit, a second input circuit, a transmission circuit, and a storage circuit;
• the first input circuit is configured to control a level of a first node in response to a first input signal,
• the output circuit is configured to provide an output signal at an output terminal under control of the level of the first node,
• the first control circuit is configured to control a level of a second node under control of the level of the first node,
• the first reset circuit is configured to reset the first node and the output terminal under control of the level of the second node,
• the second input circuit is configured to control a level of a third node in response to a selection control signal,
• the transmission circuit is configured to control the level of the first node according to the level of the third node,
• the storage circuit is electrically connected to the second node, and is configured to stabilize the level of the second node,
• the method comprises:
• controlling, by the first input circuit, the level of the first node in response to the first input signal;
• providing, by the output circuit, the output signal at the output terminal under the control of the level of the first node;
• controlling, by the first control circuit, the level of the second node under the control of the level of the first node;
• resetting, by the first reset circuit, the first node and the output terminal under the control of the level of the second node;
• controlling, by the second input circuit, the level of the third node in response to the selection control signal;
• controlling, by the transmission circuit, the level of the first node according to the level of the third node;
• and
• stabilizing, by the storage circuit, the level of the second node.