Shift register unit and method for driving shift register unit, gate drive circuit, and display device

A gate drive circuit, comprising a plurality of shift register units which are cascaded,

• wherein at least one shift register unit of the plurality of shift register units comprises:
• an input circuit, an output circuit, and a first control circuit,
• the input circuit is connected to a first node and a signal input terminal, and is configured to control a level of the first node in response to an input signal of the signal input terminal;
• the output circuit is connected to the first node, a second node, and at least one clock signal terminal, and the output circuit comprises at least one signal output terminal;
• the output circuit is configured to output at least one clock signal of the at least one clock signal terminal to the at least one signal output terminal under control of the level of the first node, and output a level of the second node to at least one of the at least one signal output terminal in a case where the first node is at a non-operating potential;
• and
• the first control circuit is connected to the first node and the second node, and is configured to control the level of the second node in response to the level of the first node.

A method for driving a shift register unit, wherein the shift register unit comprises:

• an input circuit, an output circuit, and a first control circuit,
• the input circuit is connected to a first node and a signal input terminal, and is configured to control a level of the first node in response to an input signal of the signal input terminal;
• the output circuit is connected to the first node, a second node, and at least one clock signal terminal, and the output circuit comprises at least one signal output terminal;
• the output circuit is configured to output at least one clock signal of the at least one clock signal terminal to the at least one signal output terminal under control of the level of the first node, and output a level of the second node to at least one of the at least one signal output terminal in a case where the first node is at a non-operating potential;
• the first control circuit is connected to the first node and the second node, and is configured to control the level of the second node in response to the level of the first node;
• and
• the method comprises:
• in a first phase, controlling, by the input circuit, the level of the first node in response to the input signal;
• in a second phase, outputting, by the output circuit, the at least one clock signal of the at least one clock signal terminal to the at least one signal output terminal under control of the level of the first node;
• and
• in a third phase, outputting, by the output circuit, the level of the second node to the at least one of the at least one signal output terminal in the case where the first node is at the non-operating potential, under control of the level of the second node or a first voltage.