Shift register, driving method thereof, gate driving circuit, and display device

A shift register comprising:

• an input sub-circuit,
• a reset sub-circuit,
• a potential maintenance sub-circuit,
• a node control sub-circuit,
• a first output sub-circuit, and
• a second output sub-circuit,
• wherein the input sub-circuit is connected to an input signal terminal and a first node, respectively, and configured to provide a signal of the input signal terminal to the first node under the control of the signal of the input signal terminal;
• wherein the reset sub-circuit is connected to a reset signal terminal, a reference signal terminal, and the first node, respectively, and configured to provide a signal of the reference signal terminal to the first node under the control of a signal of the reset signal terminal;
• wherein the potential maintenance sub-circuit is connected to a clock signal terminal and a second node, respectively, and configured to maintain a stable voltage difference between the clock signal terminal and the second node in response to the second node being in a floating state;
• wherein the node control sub-circuit is connected to the input signal terminal, the reset signal terminal, the reference signal terminal, the second node, and a driving signal output terminal of the shift register, respectively, and configured to:
• provide the signal of the reference signal terminal to the second node under the control of the signal of the input signal terminal,
• provide the signal of the reset signal terminal to the second node under the control of the signal of the reset signal terminal, and
• provide the signal of the reference signal terminal to the second node under the control of a signal of the driving signal output terminal;
• wherein the first output sub-circuit is connected to the clock signal terminal, the first node, and the driving signal output terminal, respectively, and configured to provide the signal of the clock signal terminal to the driving signal output terminal under the control of the signal of the first node, and maintain a stable voltage difference between the first node and the driving signal output terminal in response to the first node being in a floating state;
• and
• wherein the second output sub-circuit is connected to the reference signal terminal, the second node, and the driving signal output terminal, respectively, and configured to provide the signal of the reference signal terminal to the driving signal output terminal under the control of a signal of the second node.