Method for evaluating failure-in-time
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChin-Shen LIN, Ming-Hsien LIN, Kuo-Nan YANG, Chung-Hsing WANG
Life of this patent
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Abstract
A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.
Claims20
A failure-in-time (FIT) evaluation method for an integrated circuit (IC), comprising:
- accessing data representing a layout of the IC comprising a metal line and a plurality of vertical interconnect accesses (VIAs);
- picking a plurality of nodes along the metal line;
- dividing the metal line into a plurality of metal segments based on the nodes;
- and
- determining FIT value for each of the metal segments to verify the layout and fabricate the IC,
- wherein the number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.
A failure-in-time (FIT) evaluation method for an integrated circuit (IC), comprising:
- determining a plurality of nodes along a metal line and a plurality of vertical interconnect accesses (VIAs) from data representing a layout of the IC;
- determining a plurality of metal segments in the metal line based on the nodes;
- and
- evaluating FIT value for each of the metal segments, wherein FIT values for the metal segments are utilized to verify the layout and fabricate the IC,
- wherein it is determined that two adjacent VIAs of the VIAs are assigned to be the same node when a distance between the two adjacent VIAs is less than a width of the metal line.
A non-transitory computer-readable medium containing instructions which, when executed by a processor of a computer system, cause the processor to execute a FIT evaluation method comprising:
- determining a plurality of nodes along a metal line and a plurality of vertical interconnect accesses (VIAs) from data representing a layout of an integrated circuit (IC);
- determining a plurality of metal segments in the metal line based on the nodes;
- and
- evaluating FIT value for each of the metal segments, wherein FIT values of the metal segments are utilized to verify the layout and fabricate the IC,
- wherein it is determined that two adjacent VIAs of the VIAs are assigned to be the same node when a distance between the two adjacent VIAs is less than a width of the metal line.
Dependencies are inferred from the claim text.