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US 2021/0200928 A1Published application
MULTI-PHASE TOPOLOGY SYNTHESIS OF A NETWORK-ON-CHIP (NoC)
AssigneeArteris, Inc.
InventorsMoez CHERIF, Benoit de LESCURE
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Abstract
A process is disclosed that automatically creates a network-on-chip (NoC) very quickly using a set of constraints, which are requirements for the NoC. The process takes a set of constraints as inputs and produces a NoC with all its elements configured and a placement of such elements on the floorplan of the chip.
Claims10
A method for generation of a network, the method comprising:
- receiving constraints for the network;
- executing topology synthesis using the constraints to generate an abstract network as a solution for implementation of the network, wherein the abstract network includes abstract network elements representing simplified real elements;
- generating, using the abstract network, a real network representation of the network, wherein the real network complies with the constraints for the network;
- and
- producing an actual network, using the real network and elements from a network component library to optimize the real network based on location and pipelining in order to minimize logic congestion and to optimize timing, respectively, in the actual network.
2 more elements
A method for generation of a network, the method comprising:
- receiving constraints for the network, the constraints include an abstract network representation for the network;
- executing topology synthesis using the constraints to generate a second abstract network as a solution for implementation of the network, wherein the second abstract network includes abstract network elements;
- generating, using the second abstract network, a real network representation of the network, wherein the real network complies with the constraints for the network;
- producing an actual network using the real network and elements from a NoC component library.
1 more element
A non-transitory computer readable medium for storing code, which when executed by one or more processors, would cause the processor to:
- execute topology synthesis using a plurality of constraints;
- generate an abstract network-on-chip (NoC) as a solution for implementation of a physical NoC, wherein the abstract NoC includes abstract elements representing real elements;
- generate, using the abstract NoC, a real NoC that complies with the constraints;
- optimize the real network based on location and pipelining to produce an optimized NoC.
1 more element
Dependencies are inferred from the claim text.