System and method for predicting performance, power and area behavior of soft ip components in integrated circuit design
AssigneeArteris, Inc.
InventorBenny WINEFELD
Life of this patent
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Abstract
A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to characteristic behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.
Claims19
A method for accumulating data used as a training set for training a machine learning model capable of predicting one or more characteristics for any IP block, which has a set of input parameters, in order to optimize an IP block, the method comprising:
- determining a plurality of vectors of logical parameters for a plurality of IP arrangements;
- determining a plurality of vectors of physical parameters for the plurality of IP arrangements;
- generating a plurality of composite vectors based on the plurality of vectors of physical parameters and the plurality of vectors of logical parameters;
- synthesizing the plurality of composite vectors to generate a gate level netlist for each combination of the plurality of vectors of physical parameters and the plurality of vectors of logical parameters;
- generating a timing characterization for each gate level netlist to produce a plurality of timing characterizations;
- and
- updating the training set using data selected from a set including at least one of:
- the plurality of vectors of logical parameters;
- the plurality of vectors of physical parameters;
- the plurality of composite vectors;
- and
- the timing characterization.
A system for optimizing IP blocks comprising:
- memory for storing code;
- a processor in communication with the memory that executed the code that accumulates data used as a training set for training a machine learning model capable of predicting one or more characteristics for any IP block, which includes a set of input parameters, in order to optimize an IP block design by causing the system to:
- generate a plurality of composite vectors based on physical parameters and logical parameters;
- synthesize the plurality of composite vectors to generate a gate level netlist for each of the plurality of composite vectors;
- generate a timing characterization for each gate level netlist to produce a plurality of timing characterizations;
- add at least one acceptable result to the training set, which is selected from a set of values including:
- the plurality of vectors of logical parameters;
- the plurality of vectors of physical parameters;
- the plurality of composite vectors, and
- the timing characterization;
- and
- run a machine learning algorithm, which is trained using the training set, for an IP block to derive one or more characteristic estimations for optimizing the IP block.
A system for optimizing IP blocks comprising:
- memory for storing code;
- a processor in communication with the memory that executed the code that accumulates data used as a training set for training a machine learning model capable of predicting one or more characteristics for any IP block, which includes a set of input parameters, in order to optimize an IP block design by causing the system to:
- generate a plurality of composite vectors based on physical parameters and logical parameters;
- synthesize the plurality of composite vectors to generate a gate level netlist for each of the plurality of composite vectors;
- generate a timing characterization for each gate level netlist to produce a plurality of timing characterizations;
- run a machine learning algorithm, which is trained using the training set, on the set of input parameters;
- and
- derive one or more characteristic estimations for optimizing the IP block design used in a system-on-chip (SoC) planning tool.
Dependencies are inferred from the claim text.