System and Method for Configurable Systolic Array with Partial Read/Write

A method, comprising:

• determining a tile size for each of one or more tiles of data based on a matrix A and a matrix B;
• deriving a complete tile, an incomplete tile, or a combination thereof, based on tile size;
• and
• processing the complete tile, the incomplete tile, or the combination thereof, via a reconfigurable systolic array circuitry to derive a matrix C result, wherein processing the complete tile, the incomplete tile, or the combination thereof comprises applying a routing circuitry included in the reconfigurable systolic array circuitry and a bias addition with accumulation circuitry included in the reconfigurable systolic array circuitry, or into a combination thereof, to provide the matrix C result, wherein the first routing circuitry comprises a demultiplexer and a multiplexer circuitry connected to each other and configured to route the derivations from a first circuit block into a second circuit block, from the first circuit block into the bias addition with accumulation circuitry, or into the combination thereof, based on receiving a configuration switch signal.

An apparatus, comprising:

• a data storage configured to store a data;
• a reconfigurable systolic array circuitry;
• a decoder, of a core coupled to the reconfigurable systolic array circuitry, to decode a single instruction into a decoded one or more instructions, the one or more instructions configured to:
• communicate the data representative of a matrix A and of a matrix B from the data storage into a first circuit block comprising one or more groups of processing elements configured to process the data and to provide a derivation based on the data;
• and
• route the derivation from the first circuit block into a second circuit block, into a bias addition with accumulation circuitry, or into a combination thereof, based on switching on or off a reconfigurable routing circuitry, wherein the bias addition with accumulation circuitry is configured to add a matrix bias to an accumulated value, to a multiplication product of matrix A with matrix B, or to a combination thereof, and wherein the first circuit block, the second circuit block, the reconfigurable routing circuitry, the bias addition with accumulation circuitry, or a combination thereof, is included in the reconfigurable systolic array circuitry, wherein the reconfigurable routing circuitry comprises a demultiplexer and a multiplexer circuitry connected to each other and configured to route the derivations from the first circuit block into the second circuit block, from the first circuit block into the bias addition with accumulation circuitry, or into the combination thereof, based on receiving a configuration switch signal.