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US 2021/0200699 A1Published application
Neuromorphic memory device and method
AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Frank F Ross, Richard C Murphy
Life of this patent
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Abstract
Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.
Claims27
A memory system, comprising:
- a controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stack interface, wherein the host interface includes at least one channel, and the die stack interface includes two or more sub-channels;
- a stack of dies supported by the substrate and coupled to the two or more sub-channels;
- control logic reallocating the connections for the at least one channel to at least two sub-channels;
- and
- one or more neuromorphic layers logically coupled between one or more dies in the stack of dies and the host interface.
2 more elements
A memory system, comprising:
- a controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stack interface, wherein the host interface includes at least one channel, and the die stack interface includes two or more sub-channels;
- a stack of dies supported by the substrate and coupled to the two or more sub-channels;
- control logic reallocating the connections for the at least one channel to at least two sub-channels;
- and
- one or more neuromorphic layers logically coupled between one or more dies in the stack of dies and the host interface;
- and
- logic in the controller die to program one or more neuromorphic weights into the one or more neuromorphic layers.
4 more elements
A method, comprising
- training a neuromorphic device that is located in a memory device;
- transferring data from one or more dies in a die stack in the memory system to the neuromorphic device at a first data speed;
- locally processing the data from the die stack using the neuromorphic device;
- transferring the processed data to a host device through a buffer located in the memory system wherein the buffer is configured to provide a second data speed faster than the first data speed.
1 more element
Dependencies are inferred from the claim text.