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US 2021/0200697 A1Published application
Determining write commands for deletion in a host interface
AssigneeMicron Technology, Inc.
InventorYue Chan
Life of this patent
Estimating the term…
Abstract
An interface of a memory sub-system can determine that a particular write command received from a host has a same address as a subsequently received write command from the host. The interface can delete the particular write command if it is still in the interface or send a signal to delete the particular write command if the write command has already been provided from the interface.
Claims20
A system comprising:
- a memory device;
- a processing device coupled to the memory device and configured to control cache memory for the memory device;
- and
- an interface coupled to the processing device and configured to:
- determine that a particular write command received from a host has a same address as a subsequently received write command from the host;
- delete the particular write command in response to the particular write command not having been provided to the processing device;
- and
- signal the processing device to delete the particular write command in response to the particular write command having been provided to the processing device;
- wherein the processing device is configured to delete the particular write command in response to the signal.
6 more elements
A method comprising:
- receiving a first write command from a host;
- receiving a second write command from the host, wherein the first write command is received prior to receipt of the second write command;
- determining whether the first write command and the second write command write to a same address;
- responsive to a determination that the first write command and the second write command write to the same address, marking the first write command as erroneous utilizing error circuitry;
- and
- deleting the first write command based on the marking of the error circuitry.
3 more elements
A system, comprising:
- a memory device;
- a processing device coupled to the memory device;
- comparator circuitry coupled to the processing device and configured to:
- access a first write command, a second write command, and a third write command received from a host;
- determine that the first write command, the second write command, and the third write command write data to a same address of the memory device;
- and
- mark the first write command and the second write command as erroneous utilizing error circuitry responsive to determining that the first write command, the second write command, and the third write command write data to the same address of the memory device and that the third write command is received after the first command and second write command;
- wherein the processing device is configured to delete the first write command and the second write command in response to the first write command and the second write command being marked as erroneous.
5 more elements
Dependencies are inferred from the claim text.