Sequencer chaining circuitry
AssigneeMicron Technology, Inc.
InventorsKeith A. Benjamin, Thomas Dougherty
Life of this patent
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Abstract
A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
Claims20
A system, comprising:
- a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto;
- and
- chaining circuitry coupled to the plurality of sequencers and comprising logic to:
- responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence;
- and
- responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
A method, comprising:
- asserting a primary enable signal provided to chaining circuitry coupled to a plurality of sequencers;
- responsive to assertion of the primary enable signal, asserting, via the chaining circuitry and in accordance with a first sequence, respective sequencer enable signals provided to the plurality of sequencers;
- responsive to deassertion of the primary enable signal, deasserting, via the chaining circuitry and in accordance with a second sequence, the respective sequencer enable signals provided to the plurality of sequencers.
A system, comprising:
- a first sequencer configured to provide a first plurality of sequenced output signals;
- a second sequencer configured to provide a second plurality of sequenced output signals;
- and
- a third sequencer configured to provide a third plurality of sequenced output signals;
- wherein the first, second, and third sequencers are coupled, via chaining circuitry, in a feed-forward and a feed-backward manner such that:
- responsive to assertion of a primary enable signal provided to the chaining circuitry, sequencer enable signals provided to the respective first, second, and third sequencers are asserted in a first order;
- and
- responsive to a subsequent deassertion of the primary enable signal, the sequencer enable signals provided to the respective first, second, and third sequencers are deasserted in a second order.
Dependencies are inferred from the claim text.