Cache dynamic random access memory

A set associative cache dynamic random access memory (DRAM), comprising:

• a plurality of banks, each bank comprising a plurality of mats, each mat comprising a plurality of DRAM cells in rows and columns;
• a majority of the rows comprising rows for data as data rows, a minority of the rows comprising rows for tags, as tag rows;
• and
• a plurality of comparators each having as inputs a first plurality of address bits and a first plurality of tag information bits from the tag rows to be compared to find a cache hit and generate a second plurality of address bits to access the data information in the DRAM as one of a plurality of ways of the set associative cache.

A method of operating a set associative cache dynamic random access memory (DRAM), comprising:

• presenting a plurality of address bits of a set in the DRAM to each of a plurality of comparators in or adjacent to banks of the DRAM, wherein each bank has data rows and tag rows;
• comparing, in parallel in the plurality of comparators, the plurality of address bits and a first plurality of tag information bits from the tag rows to determine a cache hit;
• determining, based on the comparing, a second plurality of address bits;
• and
• reading from the data rows, based on the cache hit and the second plurality of address bits.