US 2021/0200679 A1 · SYSTEM AND METHOD FOR MIXED TILE-AWARE AND TILE-UNAWARE TRAFFIC THROUGH A TILE-BASED ADDRESS APERTURE

Abstract

In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

Claims16

Dependent claims

1-15. (canceled)

A method for intelligent tile-based memory bandwidth management in a portable computing device (“PCD”), the method comprising:

a tile-aware processing component detecting a data access request from a tile-unaware processing component directed to an address aperture in communication with a memory component having a tile-based address structure, wherein the data access request is associated with a linear aperture address;
and
in response to detecting the data access request, the tile-aware processing component generating a plurality of linear aperture addresses representing a plurality of tile-based addresses in an alias address region of the memory component, wherein the plurality of linear aperture addresses collectively correspond to an entire tile.

A system for intelligent tile-based memory bandwidth management in a portable computing device (“PCD”), the system comprising:

a tile-unaware processing component configured to provide a data access request directed to an address aperture in communication with a memory component having a tile-based address structure, wherein the data access request is associated with a linear aperture address;
and
a tile-aware processing component associated with the tile-unaware processing component and configured to detect the data access request and, in response to detecting the data access request, generate a plurality of linear aperture addresses representing a plurality of tile-based addresses in an alias address region of the memory component, wherein the plurality of linear aperture addresses collectively correspond to an entire tile.

Dependencies are inferred from the claim text.

Facts

Application

17/204,534Filed 17 Mar 2021

Priority

16 Aug 2019

Published

1 Jul 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/0848
Cache with multiple tag or data arrays being simultaneously accessible: partitioned cache, e.g. separate instruction and operand caches
G06F 12/0895
Caches characterised by their organisation or structure: of parts of caches, e.g. directory or tag array
G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 12/0871
For peripheral storage systems, e.g. disk cache: allocation or management of cache space

System and method for mixed tile-aware and tile-unaware traffic through a tile-based address aperture

Life of this patent

System and method for mixed tile-aware and tile-unaware traffic through a tile-based address aperture

Life of this patent

Abstract

Claims16