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US 2021/0200635 A1Published application
Nand device mixed parity management
AssigneeMicron Technology, Inc.
InventorGiuseppe Cariello
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Abstract
Devices and techniques for NAND device mixed parity management are described herein. A first portion of data that corresponds to a first data segment and a second data segment—respectively defined with respect to a structure of a NAND device—are received. A parity value using the first portion of data and the second portion of data is computed and then stored for error correction operations.
Claims22
A device comprising:
- memory;
- and
- processing circuitry to:
- compute parity data for first data and second data, the first data and second data to be written to a storage device, and the first data and second data correspond to different data segments in the storage device;
- track a relationship of the parity data to the first data and the second data in a data structure stored in the memory;
- use the data structure to decouple the parity data from the first data and the second data.
3 more elements
A storage device comprising:
- a storage array;
- a controller comprising:
- memory;
- and
- processing circuitry to:
- compute parity data for first data and second data, the first data and second data to be written to a storage device, and the first data and second data correspond to different data segments in the storage array;
- track a relationship of the parity data to the first data and the second data in a mixed-parity data structure stored in the memory;
- use the mixed-parity data structure to decouple the parity data from the first data and the second data based on an operation that uses the parity data.
5 more elements
Dependencies are inferred from the claim text.