Increased memory access parallelism using parity
AssigneeMicron Technology, Inc.
InventorQing Liang
Life of this patent
Estimating the term…
Abstract
Disclosed in some examples are memory devices which increase a parallelism of host operations of a memory device. While a first block of data from a first stripe in a first memory die is being read, blocks of data belonging to a second stripe stored in memory dies other than the first memory die are concurrently read. This includes reading the parity value of the second stripe. The parity data, along with the blocks of data from the second stripe from dies other than the first die are then used to determine the block of data of the second stripe stored in the first memory die without actually reading the value from the block in the first memory die. This reconstruction may be done in parallel with additional read operations for other data performed on the first die.
Claims22
A method of reading data from a memory device comprising:
- simultaneously causing a first portion of data to be read from a first memory die and a second portion of data to be read from a second memory die and a third portion of data to be read from a third memory die, the third portion of data including parity data for data including the second portion of data and a fourth portion of data stored in the first memory die;
- and
- reconstituting the fourth portion of data stored in the first memory die using the second portion of data and the parity data in parallel with reading a fifth portion of data from a selected memory die.
A memory device comprising:
- a multi-die memory array;
- a memory controller comprising one or more processors, and configured to perform operations comprising:
- simultaneously causing a first portion of data to be read from a first memory die and a second portion of data to be read from a second memory die and a third portion of data to be read from a third memory die, the third portion of data including parity data for data including the second portion of data and a fourth portion of data stored in the first memory die;
- and
- reconstituting the fourth portion of data stored in the first memory die using the second portion of data and the parity data of the third portion in parallel with reading a fifth portion of data being read from a selected memory die.
A machine-readable medium, storing instructions, which when executed by a controller of a memory device, cause the controller to perform operations comprising:
- simultaneously causing a first portion of data to be read from a first memory die and a second portion of data to be read from a second memory die and a third portion of data to be read from a third memory die, the third portion of data including parity data;
- and
- reconstituting a fourth portion of data stored in the first memory die using the second portion of data and the parity data in parallel with a fifth portion of data being read from the first memory die.
The machine-readable medium of claim 22, wherein the first, second, third, fourth, and fifth portions of data are Logical to Physical (L2P) translation table entries;
- and wherein the operations further comprise:
- receiving a host command;
- determining that a L2P cache in a volatile memory of the memory device does not have an entry for a logical address included in the host command;
- and
- wherein causing the first portion, second portion, third portion, and fifth portions to be read is performed responsive to determining that the L2P cache in the volatile memory of the memory device does not have the entry for the logical address included in the host command.
Dependencies are inferred from the claim text.