US 2021/0200630 A1 · APPARATUSES, SYSTEMS, AND METHODS FOR ERROR CORRECTION

Abstract

Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

Claims21

Dependent claims

An apparatus comprising:

a memory bank comprising a plurality of memory cells disposed along a word line, wherein each of the plurality of memory cells is configured to store one of a plurality of bits of information;
an error code correction (ECC) circuit configured to receive a first group of bits as part of a first read operation and a second group of bits as part of a second read operation, wherein the first group of bits arc associated with ones of the plurality of memory cells which are not adjacent other memory cells associated with the first group, and the second group of bits are associated with ones of the plurality of memory cells which are not adjacent to other memory cells associated with the second group.

Dependencies are inferred from the claim text.

Apparatuses, systems, and methods for error correction

Life of this patent

Apparatuses, systems, and methods for error correction

Life of this patent

Abstract

Claims21