# US 2021/0200619 A1 · Real-time trigger to dump an error log

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- Number: US 2021/0200619 A1
- Document ID: US20210200619A1
- Status: Published application
- Kind: A1
- Application number: 16/989,274
- Filed: 2020-08-10
- Published: 2021-07-01
- Earliest claimed: 2019-12-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Qing Liang; Jonathan Scott Parry
- Web page: https://patentgrep.com/patent/US20210200619A1

## CPC

- G06F 11/0778: {Dumping, i.e. gathering error/state information after a fault for later diagnosis}
- G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs}
- G06F 11/0775: {Content or structure details of the error report, e.g. specific table structure, specific error fields}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In various embodiments, a technique can be provided to address debug efficiency for failures found on an operational system. The approach can make use of an existing pin on a memory device with added logic to respond to a trigger signal structured different from a signal that is normally sent to the existing pin on the memory device such that the memory device performs a normal or routine function of the memory device in response to the signal. In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate the trigger signal to the memory device. In response to receiving the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.

## Claims

### Claim 1

A memory device comprising:
timing circuitry to determine occurrence of a trigger signal received on a pin of the memory device; and
a processor configured to execute instructions stored on one or more components in the memory device, which instructions, when executed by the processor, cause the memory device to perform operations, the operations comprising dumping an error log, associated with one or more error conditions, to memory of the memory device, in response to the determination of the occurrence of the trigger signal.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the pin is a pin to receive a signal for performance of a function of the memory device, with the signal being different from the trigger signal.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the trigger signal undergoes multiple toggles in a time corresponding to a specified length of time in which the signal is specified to be pulled low or specified to be pulled high.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the pin is a reset pin to receive a reset signal to identify a reset event for the memory device, with the trigger signal being different from the reset signal.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the trigger signal undergoes multiple toggles with a toggle period of approximately two hundred nanoseconds.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the operations include the memory device completing on-going tasks and saving cached host data in response to the determination of the occurrence of the trigger signal.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the instructions are stored in a dedicated portion of the memory device, the dedicated portion being separate from firmware that controls data management for the memory device for data storage.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein the dedicated portion of the memory device is a portion of a static random-access memory or a read only memory.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the error log includes hardware information and firmware information.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the error log includes one or more of a data timeout, a data mismatch, a fatal error, an initialization timeout, and a stuck system firmware identification.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the operations include transmitting the error log, dumped to the memory of the memory device, from the memory to a host.

### Claim 12

A method of preserving an error log of a memory device, the method comprising:
receiving a signal at a pin of the memory device;
determining whether the signal is a trigger signal received on the pin of the memory device, based on timing parameters of the signal; and
dumping the error log, associated with one or more error conditions, to memory of the memory device, in response to the determination of the signal being the trigger signal.

### Claim 13 (depends on 12)

The method of claim 12, wherein determining whether the received signal is the trigger signal includes determining whether the received signal undergoes multiple toggles in a time corresponding to a length of time specified for a non-error signal, assigned to the pin, to be pulled low or to be pulled high.

### Claim 14 (depends on 12)

The method of claim 12, wherein the pin is a reset pin to receive a reset signal to identify a reset event for the system, with the trigger signal being different from the reset signal.

### Claim 15 (depends on 12)

The method of claim 12, wherein determining whether the signal is the trigger signal and dumping the error log is performed by a processor of the memory device executing instructions, with the instructions stored in a dedicated portion of the memory device, the dedicated portion being separate from firmware that controls data management for storing data in the memory device.

### Claim 16

A system to interface with a memory device, the system comprising:
a processor configured to execute instructions stored on one or more components in the system, which instructions, when executed by the processor, cause the system to perform operations, the operations comprising:
detecting one or more error conditions associated with the memory device;
generating a trigger signal having specified timing parameters; and
transmitting, in response to the detection of the one or more error conditions, the trigger signal to a pin of the memory device to trigger a dump of an error log in the memory device, the pin assigned to functions of the memory device other than triggering the dump.

### Claim 17 (depends on 16)

The system of claim 16, wherein the pin is a reset pin of the memory device, the reset pin configured to receive a reset signal from the system to identify a reset event for the memory device, with the reset signal being different from the trigger signal.

### Claim 18 (depends on 17)

The system of claim 17, wherein the trigger signal is structured to undergo multiple toggles in a time corresponding to a specified length of time in which the reset signal is pulled low or pulled high.

### Claim 19 (depends on 16)

The system of claim 16, wherein the error log includes one or more of a data timeout, a data mismatch, a fatal error, an initialization timeout, and a stuck firmware identification.

### Claim 20 (depends on 16)

The system of claim 16, wherein the operations include receiving the error log, dumped to the memory of the memory device, from the memory of the memory device.