Loop exit predictor
AssigneeIntel Corporation
InventorsAlexey Yurievich SIVTSOV, Franck SALA, Jared Warner STARK, IV, Lihu RAPPOPORT
Life of this patent
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Abstract
Disclosed embodiments relate to systems and methods structured to predict a loop exit. In one example, a processor includes a branch prediction unit to determine a loop exit predictor start corresponding to a finite consistent loop, and an instruction decoder queue to: receive an iteration of the finite consistent loop corresponding to a loop exit predictor and an iteration count, replay one or more instructions of the iteration based on the iteration count, and switch to post-loop instructions responsive to a determination that a number of iterations of the finite consistent loop is equal to the iteration count.
Claims20
A processor comprising:
- a branch prediction unit to determine a loop exit predictor start corresponding to a finite consistent loop;
- and
- an instruction decoder queue to:
- receive an iteration of the finite consistent loop corresponding to a loop exit predictor and an iteration count;
- replay one or more instructions of the iteration based on the iteration count;
- and
- switch to post-loop instructions responsive to a determination that a number of iterations of the finite consistent loop is equal to the iteration count.
A method comprising:
- determining, via a branch prediction unit, a loop exit predictor start corresponding to a finite consistent loop;
- receiving, via an instruction decoder queue, an iteration of a loop exit predictor and an iteration count;
- replaying, via the instruction decoder queue, one or more instructions of the iteration based on the iteration count;
- and
- switching, via the instruction decoder queue, to post-loop instructions responsive to the number of iterations of the loop exit predictor equal to the iteration count.
A system comprising:
- a memory;
- and
- a processor comprising:
- a branch prediction unit to determine a loop exit predicator corresponding to a non-finite consistent loop;
- and
- an instruction decoder queue to:
- receive an iteration of a loop exit predictor associated with a large iteration count;
- replay one or more instructions of the iteration based on the large iteration count;
- and
- switch to post-loop instructions responsive to a prediction event.
Dependencies are inferred from the claim text.