Apparatuses, methods, and systems to precisely monitor memory store accesses

A method comprising:

• decoding an instruction into a decoded instruction with a decoder of a hardware processor core;
• executing the decoded instruction with an execution circuit of the hardware processor core to produce a resultant;
• retiring the instruction with a retirement circuit of the hardware processor core when a store request for the resultant from the execution circuit is queued into a store buffer for storage into memory;
• marking the retired instruction, by a performance monitoring circuit, for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory;
• inserting a store fence after the retired instruction, by the performance monitoring circuit, that causes previous store requests to complete within the memory;
• and
• storing the post-retirement performance information in storage of the performance monitoring circuit on detection of completion of the store request in the memory for the instruction.

A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

• decoding an instruction into a decoded instruction with a decoder of a hardware processor core;
• executing the decoded instruction with an execution circuit of the hardware processor core to produce a resultant;
• retiring the instruction with a retirement circuit of the hardware processor core when a store request for the resultant from the execution circuit is queued into a store buffer for storage into memory;
• marking the retired instruction, by a performance monitoring circuit, for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory;
• inserting a store fence after the retired instruction, by the performance monitoring circuit, that causes previous store requests to complete within the memory;
• and
• storing the post-retirement performance information in storage of the performance monitoring circuit on detection of completion of the store request in the memory for the instruction.