US 2021/0200546 A1 · HARDWARE APPARATUSES, METHODS, AND SYSTEMS FOR INDIVIDUALLY REVOCABLE CAPABILITIES FOR ENFORCING TEMPORAL MEMORY SAFETY

Abstract

Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.

Claims24

Dependent claims

A hardware processor comprising:

an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory;
and
a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.

Dependencies are inferred from the claim text.

Facts

Application

16/729,358Filed 28 Dec 2019

Published

1 Jul 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification20 codes

G06F 9/30101
Register arrangements: special purpose registers
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/35
Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes: indirect addressing
G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…

Hardware apparatuses, methods, and systems for individually revocable capabilities for enforcing temporal memory safety

Life of this patent

Hardware apparatuses, methods, and systems for individually revocable capabilities for enforcing temporal memory safety

Life of this patent

Abstract

Claims24