Apparatuses, methods, and systems for fused operations in a configurable spatial accelerator

A method comprising:

• coupling a plurality of processing elements with a network to transfer values between the plurality of processing elements, wherein a processing element of the plurality of processing elements comprises a first plurality of input queues having a multiple bit width coupled to the network, at least one first output queue having the multiple bit width coupled to the network, operation circuitry coupled to the first plurality of input queues having the multiple bit width, and a sign modification circuit coupled to the first plurality of input queues having the multiple bit width;
• storing a configuration value comprising a sign modification field in a configuration register within the processing element;
• performing a sign modification operation with the sign modification circuit on a sign bit of a value from the first plurality of input queues according to the sign modification field of the configuration value to create a sign modified value;
• performing a selected operation, specified by the configuration value, of a plurality of operations with the operation circuitry on a value from the first plurality of input queues and the sign modified value to create a resultant value;
• and
• storing the resultant value in the at least one first output queue.

A hardware processor comprising:

• a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation;
• a plurality of processing elements;
• a network between the plurality of processing elements to transfer values between the plurality of processing elements;
• and
• a processing element of the plurality of processing elements comprising:
• a first plurality of input queues having a multiple bit width coupled to the network,
• at least one first output queue having the multiple bit width coupled to the network,
• operation circuitry coupled to the first plurality of input queues having the multiple bit width,
• a sign modification circuit coupled to the first plurality of input queues having the multiple bit width, and
• a configuration register within the processing element to store a configuration value comprising a sign modification field that causes the sign modification circuit to modify a sign bit of a value from the first plurality of input queues according to the sign modification field to create a sign modified value, and the configuration value causes the operation circuitry to perform a second, selected operation of a plurality of operations on a value from the first plurality of input queues and the sign modified value to create a resultant value, and store the resultant value in the at least one first output queue.