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US 2021/0200539 A1Published application
Generic linear unit hardware accelerator
AssigneeIntel Corporation
InventorsMohamed Elmalaki, ElMoustapha Ould-Ahmed-Vall
Life of this patent
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Abstract
Embodiments of apparatuses, methods, and systems for a generic linear unit hardware accelerator are disclosed. In an embodiment, an apparatus includes a comparator, an exponential subunit, a multiplier subunit, and an adder subunit. The apparatus is to receive an input tensor, a threshold, an exponential enable, a scaling factor, and a bias factor and is to perform a transformation function on the input tensor to generate an output tensor.
Claims20
An apparatus comprising:
- a comparator;
- an exponential subunit;
- a multiplier subunit;
- and
- an adder subunit;
- wherein the apparatus is to receive an input tensor, a threshold, an exponential enable, a scaling factor, and a bias factor and is to perform a transformation function on the input tensor to generate an output tensor.
3 more elements
A method comprising:
- receiving, by a linear unit hardware accelerator, an input tensor, a threshold, an exponential enable, a scaling factor, and a bias factor;
- performing, by the linear unit hardware accelerator, a transformation function on the input tensor to generate an output tensor, wherein the transformation function is determined from a plurality of transformation functions based on the threshold, the exponential enable, the scaling factor, and the bias factor.
An apparatus comprising:
- a memory to store an instruction to specify an input tensor, a threshold, an exponential enable, a scaling factor, and a bias factor;
- and
- a linear unit hardware accelerator comprising
- a comparator;
- an exponential subunit;
- a multiplier subunit;
- and
- an adder subunit;
- wherein in response to the instruction, the linear unit hardware accelerator is to perform a transformation function on the input tensor to generate an output tensor.
6 more elements
Dependencies are inferred from the claim text.