Dual write micro-op queue

A method comprising:

• selecting, via a fetch address generator, a first thread from a micro-op cache associated with a first write port;
• selecting, via the fetch address generator, a second thread from a legacy fetch and decode pipeline associated with a second write port;
• and
• writing, to a micro-op queue, micro-ops from the first thread and the second thread in parallel.

A system comprising:

• a memory;
• and
• a processor comprising:
• a micro-op cache communicatively coupled, via a first write port, to a micro-op queue;
• and
• a legacy fetch and decode pipeline communicatively coupled, via a second write port, to the micro-op queue, the processor to:
• select, via a first thread select algorithm, a first thread from a micro-op cache associated with a first write port;
• select, via second thread select algorithm, a second thread from a legacy fetch and decode pipeline associated with a second write port;
• and
• write, to a micro-op queue, micro-ops from the first thread and the second thread in parallel.