Truth table extension for stacked memory systems
AssigneeMicron Technology, Inc.
InventorJoseph T. Pawlowski
Life of this patent
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Abstract
Techniques for extending a truth table of a stacked memory system are provided. In an example, a storage system can include a stack of first memory die configured to store data and a logic die. The logic die can include an interface circuit configured to receive multiple memory requests from an external host using a first command bus, a second command bus, and a data bus, and a controller configured to interface with the stack of first memory die to store and retrieve the data from the stack of first memory die. The logic die can include a second memory having a faster access time than devices of the stack of first memory die, and the interface circuit can directly access the second memory in response to a first memory request of the multiple of memory requests.
Claims26
A storage system comprising:
- a stack of first memory die configured to store data;
- and
- a logic die including an interface circuit configured to receive multiple memory requests from an external host using a first command bus, a second command bus, and a data bus, and a controller configured to interface with the stack of first memory die to store and retrieve the data from the stack of first memory die;
- wherein the logic die includes a second memory having a faster access time than devices of the stack of first memory die;
- and
- wherein the interface circuit is configured to directly access the second memory in response to a first memory request of the multiple of memory requests.
A method comprising:
- executing a first memory access operation of a memory device having a stack of memory die using only a first command/address bus to identify the first memory access operation;
- executing a second memory access operation of the memory device using only a second command/address bus to identify the second memory access operation;
- and
- executing a third memory access operation of the memory device using both the first command/address bus and the second command/address bus to identify the third memory access operation, wherein the third memory operation is configured to access second memory of a logic die of the memory device, wherein the second memory is different than the stack of memory die.
A logic die for a storage device, the logic die comprising:
- a first interface to communicate with a stack of memory die of the storage device;
- a second interface configured to couple with a host device;
- a second memory directly accessible from the second interface;
- and
- processing circuitry to:
- initiate a first memory access operation of the stack of memory die in response to a first request from the host device, wherein the first request uses only a first command/address bus of the second interface to identify the first memory access operation;
- initiate a second memory access operation of the stack of memory die in response to a second request from the host device, wherein the second request uses only a second command/address bus of the second interface to identify the second memory access operation;
- and
- initiate a third memory access operation of the second memory of the storage device in response to a third request from the host device, wherein the third request uses both the first command/address bus and the second command/address bus to identify the third memory access operation.
Dependencies are inferred from the claim text.