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US 2021/0200470 A1Published application
Interface read after write
AssigneeMicron Technology, Inc.
InventorYue Chan
Life of this patent
Estimating the term…
Abstract
An interface of a memory sub-system can receive a write command addressed to a first address and a read command addressed to a second address and can receive data corresponding to the write command. The interface can determine whether the first address matches the second address responsive to determining that the first address matches the second address, can drop the read command and the second address, and can provide the data to a host.
Claims20
A system comprising:
- a memory device;
- a processing device coupled to the memory device and configured to control cache memory for the memory device;
- and
- an interface coupled to the processing device and configured to:
- receive a write command addressed to a first address and a read command addressed to a second address;
- receive data corresponding to the write command;
- determine whether the first address matches the second address;
- and
- responsive to determining that the first address matches the second address:
- drop the read command and the second address;
- and
- provide the data to a host.
9 more elements
A method comprising:
- receiving, at an interface of a memory sub-system, a write command addressed to a first address and a read command addressed to a second address;
- determining whether the first address matches the second address;
- determining whether data corresponding to the write command is corrupt;
- responsive to determining that the first address matches the second address and that the data is not corrupt:
- dropping the read command and the second address;
- and
- providing the data to a host;
- and
- responsive to determining that the first address does not match the second address or that the data is corrupt, providing the read command and the second address to a processing device.
6 more elements
A system, comprising:
- a memory device;
- a processing device coupled to the memory device and configured to control cache memory for the memory device;
- an interface coupled to the processing device and configured to:
- receive a write command addressed to a first address and a first read command and a second read command addressed to a second address;
- receive data corresponding to the write command;
- responsive to determining that the first address matches the second address and that the data is not corrupt:
- drop the first read command, the second read command, and the second address;
- and
- provide the data to a host;
- and
- responsive to determining that the first address does not match the second address or that the data is corrupt, provide the first read command, the second read command. and the second address to the processing device for processing.
8 more elements
Dependencies are inferred from the claim text.