Multi-Array RAM Architecture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSanjeev Kumar Jain, Cormac Michael O'Connell
Life of this patent
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Abstract
Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.
Claims20
A memory circuit, comprising:
- a left memory array of a memory bank comprising a plurality of left memory cells;
- a right memory array of the memory bank comprising a plurality of right memory cells;
- a plurality of command input pins configured to receive a command;
- one or more array inhibiting pins configured to receive an inhibit command to block command signals to one or both of the left memory array and right memory array;
- an array control inhibitor configured to receive the inhibit command and to prevent arrival of the command to one or both of the left memory array and the right memory array based on the inhibit command.
A memory circuit, comprising:
- a left memory array of a memory bank powered by a left memory array power bus;
- a right memory array of the memory bank powered by a right memory array power bus;
- first control circuitry configured to operate the left memory array, the first control circuitry powered by a first control power bus;
- second control circuitry configured to operate the right memory array, the second control circuitry powered by a second control power bus;
- an array control inhibitor circuit configured to receive memory state control signals wherein the array control inhibitor circuit is configured to inhibit power buses according to a mode identified by the memory state control signals, said inhibiting comprising:
- inhibiting the left array power bus, the first control power bus, the right array power bus, and the second control power bus in a shutdown mode;
- inhibiting the first control power bus in a right array operation mode;
- and
- inhibiting the second control power bus in a left array operation mode.
A method of operating a multi-array memory that includes a left memory array and a right memory array of a memory bank, comprising:
- receiving a command at memory input pins;
- propagating a signal representative of the command to an array control inhibitor;
- receiving an array inhibit command on one or more other pins of the memory and providing the array inhibit command to the array control inhibitor;
- using the array control inhibitor to prevent arrival of the command to one or both of the left memory array and the right memory array based on the array inhibit command.
Dependencies are inferred from the claim text.