Memory operations with consideration for wear leveling

A method for operating a memory controller, comprising:

• receiving a traffic dataset comprising a plurality of data indicative of access frequencies for a plurality of portions of a memory communicatively accessed by the memory controller, wherein the traffic dataset is generated while the memory controller uses a first assignment that causes a first logical address to correspond to a first physical address for a first portion of the plurality of portions;
• determining that the first portion is accessed sequential to a second portion of the plurality of portions;
• generating a second assignment that causes the first logical address to correspond to a third physical address for a third portion;
• and
• storing, in a buffer memory configured to store the first assignment, the second assignment to overwrite the first assignment in the buffer memory.

A semiconductor device, comprising:

• a memory comprising a first portion, a second portion, and a third portion, wherein the first portion and the third portion are configured to be accessed at least partially in parallel;
• and
• a memory controller comprising a buffer memory, wherein the memory controller is configured to:
• determine that the first portion is accessed sequential to an access of the second portion;
• in response to determining that the first portion is accessed sequential to the access of the second portion, generate a plurality of logical-to-physical tables that each comprise an assignment of a logical address to be used to access the third portion, wherein the logical address was used at a previous time to access the first portion;
• select a first logical-to-physical table from the plurality of logical-to-physical tables based at least in part on an evaluation of memory access latencies for each of the plurality of logical-to-physical tables;
• and
• store, in the buffer memory, the first logical-to-physical table as to overwrite a second logical-to-physical table.