Memory system with block rearrangement to secure a free block based on read valid first and second data

A memory system comprising:

• a first interface circuit configured to communicate with a host device, the host device including a first semiconductor memory;
• a nonvolatile second semiconductor memory including a plurality of blocks including a first block, a second block, and a third block, each of the blocks being a unit of an erase operation of the nonvolatile second semiconductor memory;
• a second interface circuit configured to connect to the nonvolatile second semiconductor memory;
• and
• a controller circuit configured to, in a case that the memory system is connected to the host device via the first interface circuit:
• read a valid first data from the first block via the second interface circuit;
• write the read first data into an area of the first semiconductor memory of the host device via the first interface circuit, the area having been designated by the host device for storing data from the memory system;
• read a valid second data from the second block via the second interface circuit;
• write the read second data into the area of the first semiconductor memory via the first interface circuit;
• read the first data and the second data from the area of the first semiconductor memory via the first interface circuit;
• and
• write the read first data and the read second data into the third block via the second interface circuit.

A storage system comprising:

• a host device including a first semiconductor memory;
• and
• a memory system, including:
• a first interface circuit configured to communicate with the host device;
• a nonvolatile second semiconductor memory including a plurality of blocks including a first block, a second block, and a third block, each of the blocks being a unit of an erase operation of the nonvolatile second semiconductor memory;
• a second interface circuit configured to connect to the nonvolatile second semiconductor memory;
• and
• a controller circuit configured to, in a case that the memory system is connected to the host device via the first interface circuit:
• read a valid first data from the first block via the second interface circuit;
• write the read first data into an area of the first semiconductor memory of the host device via the first interface circuit, the area having been designated by the host device for storing data from the memory system;
• read a valid second data from the second block via the second interface circuit;
• write the read second data into the area of the first semiconductor memory via the first interface circuit;
• read the first data and the second data from the area of the first semiconductor memory via the first interface circuit;
• and
• write the read first data and the read second data into the third block via the second interface circuit.

A method for a memory system capable of communicating with a host device including a first semiconductor memory, the memory system including a nonvolatile second semiconductor memory including a plurality of blocks including a first block, a second block, and a third block, each of the blocks being a unit of an erase operation of the nonvolatile second semiconductor memory, the method comprising:

• executing a process of, in a case that the memory system is connected to the host device via a first interface circuit:
• reading a valid first data from the first block via a second interface circuit;
• writing the read first data into an area of the first semiconductor memory of the host device via the first interface circuit, the area having been designated by the host device for storing data from the memory system;
• reading a valid second data from the second block via the second interface circuit;
• writing the read second data into the area of the first semiconductor memory via the first interface circuit:
• reading the first data and the second data from the area of the first semiconductor memory via the first interface circuit;
• and
• writing the read first data and the read second data into the third block via the second interface circuit.