Managing reduced power memory operations
AssigneeMicron Technology, Inc.
InventorsQing Liang, Jonathan Scott Parry, David Aaron Palmer, Stephen Hanna
Life of this patent
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Abstract
A memory device includes a hardware suspend mechanism configured to place a component of a memory controller into a lower power mode while a memory operation is being completed. A timer is provided to wakeup the CPU out of the lower power mode; and hardware interrupts can be used in determining to either enter or wake from the lower power mode. Memory monitoring circuitry is provided to estimate the duration of memory operations; and timers are provided to wake the component in the absence of hardware interrupts or additional commands.
Claims22
A memory device comprising:
- a memory array;
- and
- a memory controller configured to receive commands from a host device, the memory controller including processing circuitry including one or more processors, and is configured to perform operations including:
- initiating a first memory management operation in the memory array;
- placing at least one component of the memory controller in a lower power mode during the first memory management operation;
- setting a wakeup time based on a predicted completion time of the first memory management operation;
- and
- toggling the memory controller out of the lower power mode upon the occurrence of at least one of a wake event and expiration of the wakeup time.
A method of managing power usage of a memory device comprising a memory array and a memory controller configured to receive instructions from a host device, the method including:
- initiating a first memory management operation in the memory array;
- placing at least one component of the memory controller in a lower power mode during the first memory management operation;
- setting a wakeup time based on a predicted completion time of the first memory management operation;
- and
- toggling the memory controller out of the lower power mode upon the occurrence of at least one of a wake event and expiration of the wakeup time.
At least one non-transitory device-readable storage medium comprising instructions that, when executed by one or more processors of a memory controller, cause the one or more processors to perform operations comprising:
- initiating a first memory management operation in a memory array;
- placing at least one component of the memory controller in a lower power mode during the first memory management operation;
- setting a wakeup time based on a predicted completion time of the first memory management operation;
- and
- toggling the memory controller out of the lower power mode upon the occurrence of at least one of a wake event and expiration of the wakeup time.
Dependencies are inferred from the claim text.