System, Apparatus And Method For Responsive Autonomous Hardware Performance State Control Of A Processor
AssigneeIntel Corporation
InventorsHisham Abu Salah, Efraim Rotem, Eliezer Weissmann, Yoni Aizik, Daniel D. Lederman
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Abstract
In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a first core to execute instructions;
- and
- a power controller coupled to the first core, the power controller to control power consumption of the processor, wherein in response to an update to an energy performance preference hint received from an operating system, the power controller is to update a performance state of the first core autonomously to the operating system, the updated performance state having an operating frequency based at least in part on a target utilization value.
A system comprising:
- a processor comprising:
- a plurality of cores to execute instructions;
- a power controller coupled to the plurality of cores, wherein the power controller comprises:
- a first control circuit to receive a preference hint generated from an operating system and calculate a target operating frequency for at least a first core of the plurality of cores based at least in part on the preference hint;
- and
- a second control circuit to receive an indication of the target operating frequency and in response to the indication, cause a first clock circuit to output a clock signal to cause the first core to operate at the target operating frequency, wherein the second control circuit is to independently control a performance state of at least some of the plurality of cores;
- and
- a management controller coupled to the processor, the management controller to perform platform level power management and issue one or more power management requests to the processor.
The system of claim 13, further comprising a storage to store a table having a plurality of entries, each of the plurality of entries to associate a preference hint with a target utilization value, the first control circuit to use the preference hint to access a first target utilization value stored in a first entry of the plurality of entries.
A machine-readable medium having stored thereon instructions, which if performed by a machine, cause the machine to perform a method comprising:
- receiving, in a controller of a processor, an energy performance preference hint from an operating system;
- determining a target utilization value using the energy performance preference hint;
- calculating a target operating frequency based at least in part on the target utilization value, an average utilization value and an average operating frequency;
- and
- causing at least one core of the processor to operate at a first performance state, the first performance state having the target operating frequency.
Dependencies are inferred from the claim text.