Power delivery timing for memory
AssigneeMicron Technology, Inc.
InventorsKeith A. Benjamin, Thomas Dougherty
Life of this patent
Estimating the term…
Abstract
A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.
Claims20
An apparatus, comprising:
- a memory array;
- sensing circuitry;
- control circuitry coupled to the memory array and the sensing circuitry and configured to:
- receive an access command targeting a particular address within the memory array;
- responsive to determining that the received access command is not authorized to access the particular address, update a plurality of data lines configured to provide data from the memory array responsive to receipt of access commands,
- wherein the plurality of data lines coupled to the sensing circuitry are updated by resetting a plurality of keeper latches coupled to the plurality of data lines to update the plurality of data lines.
An apparatus, comprising:
- a memory array;
- sensing circuitry;
- a plurality of latches, wherein each of the plurality of latches comprises a plurality of AND gates and a plurality of NOR gates;
- and
- control circuitry coupled to the memory array and the sensing circuitry and configured to:
- receive an access command targeting a particular address within the memory array;
- responsive to determining that the received access command is not authorized to access the particular address, update a plurality of data lines configured to provide data from the memory array responsive to receipt of access commands,
- wherein the plurality of data lines coupled to the sensing circuitry are updated by resetting a plurality of latches coupled to the plurality of data lines to update the plurality of data lines.
A method, comprising:
- receiving an access command targeting a particular address within a memory array;
- determining that the received access command is not authorized to access the particular address;
- responsive to determining that the received access command is not authorized to access the particular address, updating a plurality of data lines configured to provide data from the memory array responsive to receipt of access commands;
- wherein the plurality of data lines are updated by resetting a plurality of latches coupled to the plurality of data lines to update the plurality of data lines;
- and
- wherein the plurality of latches comprise a first AND gate, a second AND gate, a first NOR gate, and a second NOR gate.
Dependencies are inferred from the claim text.