Mid power mode for an oscillator

A method to generate different clock signals of different qualities in a device, the method comprising:

• determining whether the device is operating in a mid power mode or a high power mode;
• in response to the determining that the device is operating in the mid power mode, controlling oscillator circuitry to cause the oscillator circuitry to consume a lower amount of power, such that the oscillator circuitry generates a lower quality clock signal;
• and
• in response to the determining that the device is operating in the high power mode, controlling the oscillator circuitry to cause the oscillator circuitry to consume a higher amount of power, such that the oscillator circuitry generates a higher quality clock signal,
• wherein the lower amount of power and the higher amount of power are different from one another.

A clock signal generation system for a device, comprising:

• generator circuitry configured to generate a sinusoidal signal having a predetermined frequency;
• two-level shaper circuitry configured to shape the sinusoidal signal to generate a first clock signal or a second clock signal, wherein the first clock signal is characterized by a lower quality than the second clock signal;
• multi-mode regulator circuitry configured to provide a selected one of a lower level of power or a higher level of power to the generator circuitry and the two-level shaper circuitry;
• and
• control circuitry configured to control the generator circuitry, the two-level shaper circuitry, and the multi-mode regulator circuitry, based on a mode selection, to generate and output a selected one of the first clock signal or the second clock signal as an output clock signal.

Oscillator circuitry, comprising:

• control circuitry configured to determine a mode of operation of a device that uses clock signals generated by the oscillator circuitry;
• multi-mode regulator circuitry configured to output either a mid level of power or a high level of power based at least on the determined mode of operation, wherein the multi-mode regulator circuitry consumes a lower amount of power when outputting the mid level of power and a higher amount of power when outputting the high level of power;
• and
• wherein the oscillator circuitry generates a first clock signal having a lower quality in response to the mid level of power and a second clock signal having a higher quality in response to the high level of power.