Multi-phase clock signal phase difference detection and calculation circuit and method and digital phase modulation system

A digital-to-time conversion system, comprising:

• a decoder;
• a multi-phase clock signal generator, which outputs clock signals with different phases included in one clock signal;
• and
• a multi-phase clock signal phase difference detection and calculation circuit, which detects and calculates a phase difference between each two of a plurality of phase clock signals, wherein the multi-phase clock signal phase difference detection and calculation circuit comprises:
• an auxiliary digital-to-time conversion circuit;
• a main digital-to-time conversion circuit;
• a phase detector,
• wherein an output terminal of the auxiliary digital-to-time conversion circuit and an output terminal of the main digital-to-time conversion circuit are respectively connected to an input terminal of the phase detector;
• and
• a state machine,
• wherein an output terminal of the phase detector is connected to an input terminal of the state machine,
• wherein an output terminal of the state machine is connected to a control terminal of the auxiliary digital-to-time conversion circuit and a control terminal of the main digital-to-time conversion circuit,
• wherein the auxiliary digital-to-time conversion circuit selects one of a first phase clock signal and a second phase clock signal and outputs an auxiliary clock signal under the control of the state machine, and adjusts the phase of the auxiliary clock signal,
• wherein the main digital-to-time conversion circuit selects one of a first clock signal and a second clock signal under the control of the state machine,
• wherein the phase detector compares the phase of the auxiliary clock signal with the phase of a first target clock signal output by the main digital-to-time conversion circuit based on the second phase clock signal as input, and outputs a first phase detection result signal,
• wherein the state machine adjusts one of the auxiliary digital-to-time conversion circuit and the main digital-to-time conversion circuit according to the first phase detection result signal until the phase difference between the auxiliary clock signal and the first target clock signal is zero and keeps an adjusted auxiliary clock signal unchanged,
• wherein the phase detector compares the phase of the adjusted auxiliary clock signal with the phase of a second target clock signal output by the main digital-to-time conversion circuit based on the first phase clock signal as input, and outputs a second phase detection result signal,
• wherein the state machine adjusts a delay control signal according to the second phase detection result signal to adjust the phase of the second target clock signal until the adjusted auxiliary clock signal and the second target clock signal have a phase difference of zero according to the phase detector, and then the amount of phase adjustment of the second target clock signal is identified as a phase difference between the first phase clock signal and the second phase clock signal;
• wherein the decoder receives the phase difference and decodes based on the phase difference to cancel out the phase mismatch in the digital domain.

A method of detecting and calculating phase differences of multi-phase clock signals, comprising:

• receiving, by an auxiliary digital-to-time conversion circuit, one of a first phase clock signal and a second phase clock signal, and outputting an auxiliary clock signal;
• receiving, by a main digital-to-time conversion circuit, a second phase clock signal, and outputting a first target clock signal;
• adjusting one of the auxiliary digital-to-time conversion circuit and the main digital-to-time conversion circuit until the phase difference between the auxiliary clock signal and the first target clock signal is zero, and keeping the adjusted auxiliary clock signal unchanged;
• receiving, by the main digital-to-time conversion circuit, the first phase clock signal again and outputting a second target clock signal;
• adjusting the phase of the second target clock signal until the phase difference between the second target clock signal and the adjusted auxiliary clock signal is zero;
• and
• identifying the amount of phase adjustment of the second target clock signal as a calculated phase difference between the first phase clock signal and the second phase clock signal.