# US 2021/0176005 A1 · Reduced power transmitter during standby mode

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- Number: US 2021/0176005 A1
- Document ID: US20210176005A1
- Status: Published application
- Kind: A1
- Application number: 16/936,065
- Filed: 2020-07-22
- Published: 2021-06-10
- Earliest claimed: 2019-12-05
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Sanjay PENNAM; Vamsi Krishna KANDALLA; Brahmendra Reddy YATHAM; Shailesh WARDHEN; Jaiganesh BALAKRISHNAN; Jawaharlal TANGUDU
- Web page: https://patentgrep.com/patent/US20210176005A1

## CPC

- H04L 1/0044: {specially adapted for power saving}
- H04B 1/04: Circuits
- H04L 1/0042: {Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence)}
- H04L 1/0047: {Decoding adapted to other signal detection operation (in conjunction with sequence estimation or equalization H04L25/03286)}
- H04L 1/0061: {Error detection codes}
- H04L 25/03866: {using scrambling}
- H04L 25/4908: {using mBnB codes}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04B: TRANSMISSION

## Abstract

A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

## Claims

### Claim 1

A transmitter, comprising:
a data stream encoder layer having an output;
a pattern generator having a bit pattern output; and
a first multiplexer having first and second inputs and a first multiplexer output, the first input coupled to the output of the data stream encoder layer, and the second input coupled to the bit pattern output of the pattern generator;
wherein, while at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

### Claim 2 (depends on 1)

The transmitter of claim 1, wherein the data stream encoder layer provides an encoder state value to the pattern generator and the pattern generator uses the encoder state value provided by the data stream encoder layer to provide a bit pattern to the multiplexer.

### Claim 3 (depends on 2)

The transmitter of claim 2, wherein:
upon powering up the data stream encoder layer, the pattern generator is configured to provide its current encoder state value to the data stream encoder layer;
the control signal to the first multiplexer is configured to select the first input of the first multiplexer;
the data stream encoder layer uses the pattern generator's current encoder state value to provide a bit pattern on the data stream encoder layer's output.

### Claim 4 (depends on 2)

The transmitter of claim 2, wherein the encoder state value is a running disparity (RD) value.

### Claim 5 (depends on 1)

The transmitter of claim 1, wherein the pattern generator includes:
a second multiplexer having first and second inputs, a selection input, and an output, wherein a first bit pattern is coupled to the first input of the second multiplexer and a second bit pattern is coupled to the second input of the second multiplexer; and
a random number generator having an output coupled to the selection input of the second multiplexer.

### Claim 6 (depends on 1)

The transmitter of claim 1, wherein:
the data stream encoder layer is a first data stream encoder layer;
the transmitter includes a second data stream encoder layer; and
the pattern generator is configured to provide bit patterns for the first and second encoder layers.

### Claim 7 (depends on 6)

The transmitter of claim 6, wherein the transmitter implements encoder state values for the first and second data stream encoder layers, and the transmitter further comprises:
a second multiplexer having first and second inputs, a selection input, and an output;
a third multiplexer having first and second inputs, a selection input, and an output; and
an aligner having first and second aligner outputs, the first aligner output coupled to the selection input of the second multiplexer, and the second aligner output coupled to the selection input of the third multiplexer, the aligner configured to force the encoder state values of the first and second data stream encoder layers to be the same.

### Claim 8 (depends on 1)

The transmitter of claim 1, wherein:
the data stream encoder layer includes an error-detecting code generator configured to calculate error-detecting codes for data to be transmitted by the transmitter;
the error-detecting code generator is configured to provide its current error-detecting code to the pattern generator upon transition of the data stream encoder layer to a standby mode; and
the pattern generator generates a first bit pattern on its bit pattern output using the current error-detecting code.

### Claim 9 (depends on 8)

The transmitter of claim 8, wherein the pattern generator includes:
a second multiplexer having first and second inputs, a selection input, and an output, wherein bit patterns are provided to the first and second inputs of the second multiplexer;
a third multiplexer having first and second inputs, a selection input, and an output, wherein error-detecting codes corresponding to the first and second bit patterns are provided to the first and second inputs of the third multiplexer; and
a random number generator having an output coupled to the selection inputs of the second and third multiplexers.

### Claim 10 (depends on 9)

The transmitter of claim 9, wherein the first and second bit patterns comprise seed values.

### Claim 11 (depends on 8)

The transmitter of claim 8, wherein, during the standby mode of the data stream encoder layer, the pattern generator generates a second bit pattern on its bit pattern output, the second bit pattern includes an error-detecting code.

### Claim 12 (depends on 11)

The transmitter of claim 11, wherein the data stream encoder layer includes a scrambler and, upon transition from the standby mode to an active mode of the data stream encoder layer, the pattern generator provides a third error-detecting code to the error-detecting code generator, and the data stream encoder layer generates a bit pattern on its output that includes the third error-detecting code and data from the scrambler.

### Claim 13 (depends on 8)

The transmitter of claim 8, further including:
a first scrambler having an input and an output, the output is coupled to the first input of the first multiplexer; and
an aligner having an input and an output, the aligner configured to provide a seed value to the scrambler.

### Claim 14 (depends on 13)

The transmitter of claim 13, wherein:
the data stream encoder layer is a first data stream encoder layer configured to implement a first data stream; and
the transmitter includes a second data stream encoder layer configured to implement a second data stream, the second data stream encoder layer including a scrambler;
the aligner is configured to provide the same seed value to the scramblers of the first and second data stream encoder layers; and
the pattern generator is configured to provide bit patterns to the first and second data stream encoder layers.

### Claim 15 (depends on 1)

The transmitter of claim 1, wherein the transmitter implements the JESD204B or the JESD204C protocol.

### Claim 16

A transmitter, comprising:
a data stream encoder layer having an output;
a pattern generator having a bit pattern output, the pattern generator including a random number generator, and the pattern generator is configured to provide bit patterns on its bit pattern output based, at least in part, on a random number produced by the random number generator; and
a first multiplexer having first and second inputs and a first multiplexer output, the first input coupled to the output of the data stream encoder layer, and the second input coupled to the bit pattern output of the pattern generator;
wherein, while at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

### Claim 17 (depends on 16)

The transmitter of claim 16, wherein the data stream encoder layer provides an encoder state value to the pattern generator and the pattern generator uses the encoder state value provided by the data stream encoder layer to provide a bit pattern to the multiplexer.

### Claim 18 (depends on 16)

The transmitter of claim 16, wherein the encoder state value is a running disparity (RD) value.

### Claim 19 (depends on 16)

The transmitter of claim 16, wherein the pattern generator includes:
a second multiplexer having first and second inputs, a selection input, and an output, wherein a first bit pattern is coupled to the first input of the second multiplexer and a second bit pattern is coupled to the second input of the second multiplexer; and
the random number generator has an output coupled to the selection input of the second multiplexer.

### Claim 20 (depends on 19)

The transmitter of claim 19, wherein:
the first bit pattern includes a first bit and a last bit;
the second bit pattern includes a first bit and a last bit; and
the first bit of the first bit pattern matches the last bit of the second bit pattern, and the last bit of the first bit pattern matches the first bit of the second bit pattern.

### Claim 21 (depends on 16)

The transmitter of claim 16, wherein:
the data stream encoder layer includes an error-detecting code generator configured to calculate error-detecting codes for data to be transmitted by the transmitter;
the error-detecting code generator is configured to provide its current error-detecting code to the pattern generator upon transition of the data stream encoder layer to a standby mode; and
the pattern generator generates a first bit pattern on its bit pattern output using the current error-detecting code.

### Claim 22

A method, comprising:
activating a pattern generator;
providing a control parameter from a data stream encoder layer of a transmitter to the pattern generator;
powering down the transmitter's data stream encoder layer;
generating, by the pattern generator, a first bit pattern based, at least in part, on the control parameter provided from the data stream encoder layer; and
providing the first bit patterns from the pattern generator through a serializer of the transmitter while the transmitter's data stream encoder layer is in a standby mode.

### Claim 23 (depends on 22)

The method of claim 22, wherein providing the control parameter includes providing a running disparity (RD) value.

### Claim 24 (depends on 22)

The method of claim 22, wherein providing the control parameter includes providing an error-detecting code.

### Claim 25 (depends on 22)

The method of claim 22, further comprising:
upon initiating a transition of the data stream encoder layer from the standby mode to an active mode, providing a second control parameter from the pattern generator to the data stream encoder layer;
generating output data, by the data stream encoder layer, based, at least in part, on the second control parameter from the pattern generator; and
providing the output data from the data stream encoder layer to the transmitter while the transmitter's data stream encoder layer is in the active mode.

### Claim 26 (depends on 25)

The method of claim 25, wherein the control parameter is a running disparity (RD) value or an error-detecting code.

### Claim 27 (depends on 22)

The method of claim 22, wherein the transmitter implements first and second encoder layers, and the method further includes providing the first bit patterns from the pattern generator to the first and second encoder layers while the first and second encoder layers are in the standby mode.

### Claim 28 (depends on 27)

The method of claim 27, further comprising, upon transitioning the first and second data stream encoder layers from an active mode to a standby mode, the method includes forcing encoder states of the first and second encoder layers to a same state.

### Claim 29 (depends on 27)

The method of claim 27, further comprising, upon transitioning the first and second data stream encoder layers from an active mode to a standby mode, the method includes providing an error code from an error-detecting code generator to the pattern generator.
