# US 2021/0175902 A1 · Variable read error code correction

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- Number: US 2021/0175902 A1
- Document ID: US20210175902A1
- Status: Published application
- Kind: A1
- Application number: 17/181,712
- Filed: 2021-02-22
- Published: 2021-06-10
- Earliest claimed: 2018-12-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Xiangang Luo; Ting Luo
- Web page: https://patentgrep.com/patent/US20210175902A1

## CPC

- H03M 13/1128: {Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations}
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.

## Claims

### Claim 1

A device for variable read error code correction (ECC), the controller comprising:
a hardware interface to receive bits from a memory in response to a read that is one type of several types of read; and
processing circuitry configured to perform a low-density parity check (LDPC) on the bits based on the type by:
performing a number of LDPC decodes that is less than a total number of possible LDPC decodes; and
signaling a failure for the read based on reaching the number of LDPC decodes.

### Claim 2 (depends on 1)

The device of claim 1, wherein the hardware interface is configured to receive bits from a second read, the second read of the one type; and wherein the processing circuitry is configured to:
address errors in the bits from the third read in fewer LDPC decodes than the number of LDPC decodes; and
signal a read success in response to addressing the errors in the bits from the third read in fewer LDPC decodes than the number of LDPC decodes.

### Claim 3 (depends on 1)

The device of claim 1, wherein the interface is configured to receive the bits from a second read, the second read of a second type from the several types; and wherein the processing circuitry is configured to:
perform second LDPC iterations up to a second number of LDPC decodes, the second number greater that the number of LDPC decodes and less than the total number of possible LDPC decodes; and
signal a second read failure in response to the second LDPC iterations reaching the second number of LDPC decodes.

### Claim 4 (depends on 3)

The device of claim 3, wherein the second type is a read-error type.

### Claim 5 (depends on 4)

The device of claim 4, wherein the read-error type is signaled with a set of bits in a hardware read interface of the device to a host device or a controller of the device.

### Claim 6 (depends on 5)

The device of claim 5, wherein the set of bits is stored by the host or the controller in a register of the hardware read interface.

### Claim 7 (depends on 4)

The device of claim 4, wherein the read-error type is signaled within a read command from a host device or a controller of the device.

### Claim 8 (depends on 3)

The device of claim 3, wherein the number of LDPC decodes is a multiple of the number of LDPC decodes.

### Claim 9 (depends on 8)

The device of claim 8, wherein the multiple is two or three times.

### Claim 10 (depends on 3)

The device of claim 3, wherein the second read is a result of a read error handling operation following the read failure.

### Claim 11 (depends on 3)

The device of claim 3, wherein, to signal the second read failure in response to the second LDPC iterations reaching the second number of LDPC decodes, the processing circuitry is configured to provoke a read trial operation.

### Claim 12 (depends on 1)

The device of claim 1, wherein the one type is a performance type.

### Claim 13 (depends on 12)

The device of claim 12, wherein the one type is an unflagged read.

### Claim 14 (depends on 1)

The device of claim 1, wherein the several types of read each have a unique number of LDPC decodes that are equal to or less than the total number of possible LDPC decodes.

### Claim 15 (depends on 1)

The device of claim 1, wherein the number of decodes implements a performance change in read throughput for the device.

### Claim 16 (depends on 15)

The device of claim 15, wherein the performance change occurs at between thirty-five error bits per one thousand bits and forty-five error bits per one thousand bits inclusive.

### Claim 17 (depends on 1)

The device of claim 1, wherein the device is included in a package with the memory.

### Claim 18 (depends on 1)

The device of claim 1, wherein the device is included in a controller for the memory.

### Claim 19 (depends on 1)

The device of claim 1, wherein the memory is a solid state memory.

### Claim 20 (depends on 19)

The device of claim 19, wherein the solid state memory is a NAND flash memory.