# US 2021/0175868 A1 · Circuits and Methods for Maintaining Gain for a Continuous-Time Linear Equalizer

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- Number: US 2021/0175868 A1
- Document ID: US20210175868A1
- Status: Published application
- Kind: A1
- Application number: 17/099,183
- Filed: 2020-11-16
- Published: 2021-06-10
- Earliest claimed: 2019-12-06
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Miao LI; Li SUN; Hao LIU
- Web page: https://patentgrep.com/patent/US20210175868A1

## CPC

- H03F 1/301: {in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence)}
- H03G 5/165: {Equalizers; Volume or gain control in limited frequency bands}
- H03F 3/04: with semiconductor devices only
- H03F 3/45197: {Pl types (H03F3/45224, H03F3/45251 take precedence)}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03F 3/45636: {by using feedback means (H03F3/45744 takes precedence)}
- H03G 1/0029: {using field-effect transistors [FET]}
- H03G 3/30: in amplifiers having semiconductor devices
- H04L 25/0272: {Arrangements for coupling to multiple lines, e.g. for differential transmission}
- H04L 25/0292: {Arrangements specific to the receiver end}
- H04L 25/0294: {Provision for current-mode coupling}
- H04L 25/03878: {Line equalisers; line build-out devices}
- H03F 1/302: {in bipolar transistor amplifiers (H03F1/303, H03F1/305, H03F1/307 take precedence)}
- H03F 2200/453: Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
- H03F 2200/555: A voltage generating circuit being realised for biasing different circuit elements
- H03F 2203/45244: the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
- H03F 2203/45286: the temperature dependence of a differential amplifier being controlled
- H03F 2203/45288: Differential amplifier with circuit arrangements to enhance the transconductance
- H03F 2203/45424: the CMCL comprising a comparator circuit
- H03F 2203/45434: the CMCL output control signal being a voltage signal
- H03G 5/28: having semiconductor devices
- H03G 2201/103: being an amplifying element
- H03F: AMPLIFIERS
- H03G: CONTROL OF AMPLIFICATION
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.

## Claims

### Claim 1

A receiver circuit comprising:
an analog equalizer including a first transistor in series with a first resistor and with a first current source; and
a bias circuit including a second transistor in series with a second current source, the bias circuit further including a second resistor between the second current source and a third transistor, a first operational amplifier (op amp) having a first input coupled to a gate of the second transistor and a second input coupled to a source of the third transistor, a second op amp having a third input coupled to a gate of the second transistor and a fourth input coupled to a drain of the second transistor, an output of the second op amp providing a gate voltage to the first current source and to the second current source.

### Claim 2 (depends on 1)

The receiver circuit of claim 1, further comprising:
an additional bias circuit having a third op amp providing a gate voltage for a fourth transistor and receiving a reference voltage and feedback voltage from the fourth transistor, wherein the gate voltage for the fourth transistor is provided to a fifth transistor, which is in series with the first transistor and the first current source.

### Claim 3 (depends on 1)

The receiver circuit of claim 1, wherein the second transistor is a replica of the first transistor, and wherein the second current source is a replica of the first current source.

### Claim 4 (depends on 1)

The receiver circuit of claim 1, wherein the second resistor comprises a replica of the first resistor.

### Claim 5 (depends on 1)

The receiver circuit of claim 1, wherein the gate of the second transistor is coupled to an output of a bandgap voltage generator.

### Claim 6 (depends on 1)

The receiver circuit of claim 1, wherein the first transistor includes a gate coupled to a data input from a transmission line.

### Claim 7 (depends on 1)

The receiver circuit of claim 1, wherein the first transistor and the first current source are part of a first leg of a current mirror having a second leg, wherein the first leg is coupled to a first part of a differential data signal, and wherein the second leg is coupled to a second part of the differential data signal.

### Claim 8 (depends on 1)

The receiver circuit of claim 1, wherein the first transistor is disposed between the first resistor and the first current source.

### Claim 9 (depends on 1)

The receiver circuit of claim 1, wherein the first current source is disposed between the first transistor and ground.

### Claim 10 (depends on 1)

The receiver circuit of claim 1, wherein bias circuit includes a current mirror, and wherein the second transistor is disposed within a first leg of the current mirror and the third transistor and the second resistor are disposed within a second leg of the current mirror, further wherein the second current source is disposed between the second resistor and ground.

### Claim 11

A method for operating an equalizer circuit, the method comprising:
at a first bias circuit having a first transistor and a second transistor arranged in separate legs of a current mirror, maintaining a drain voltage of the first transistor and a drain voltage of the second transistor equal to a gate voltage of the first transistor;
generating a current by a first current source in series with legs of the current mirror, wherein a gate voltage of the first current source is provided by a first operational amplifier (op amp) disposed between a gate of the first transistor and a drain of the second transistor; and
applying the gate voltage to a second current source within the equalizer circuit.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
maintaining a transconductance times resistance (gm*R) of the first bias circuit constant over a range of process corners, operating voltages and operating temperatures; and
maintaining a gm*R of the equalizer circuit to be equal to the gm*R of the first bias circuit.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
at a second bias circuit, generating a bias voltage for a gate of a third transistor within the equalizer circuit, wherein generating the bias voltage includes maintaining a common mode voltage of the equalizer circuit to be the same as a common mode voltage of the second bias circuit.

### Claim 14

A semiconductor chip comprising:
a first bias circuit having a first transistor and a second transistor arranged in a first current mirror, the first bias circuit further having a first current source coupled to the first transistor and the second transistor, the first bias circuit further having a first operational amplifier (op amp) coupled to a drain of the second transistor and a gate of the first transistor and coupled to output a first bias voltage to a gate of the first current source;
a second bias circuit having a second op amp coupled to output a second bias voltage to a gate of a third transistor; and
an equalizer circuit having a fourth transistor and a fifth transistor are arranged in a second current mirror, the fourth transistor being in series with a second current source, the second current mirror coupled to a power rail by a sixth transistor, wherein the second current source is coupled to the first bias voltage, and wherein the sixth transistor is coupled to the second bias voltage.

### Claim 15 (depends on 14)

The semiconductor chip of claim 14, comprising a system on chip (SOC) having a multi-core processor configured to communicate with a memory chip via the equalizer circuit.

### Claim 16 (depends on 14)

The semiconductor chip of claim 14, comprising a memory chip configured to communicate with a system on chip (SOC) via the equalizer circuit.

### Claim 17 (depends on 14)

The semiconductor chip of claim 14, wherein the first transistor is a replica of the fourth transistor, and wherein the first current source is a replica of the second current source.

### Claim 18 (depends on 14)

The semiconductor chip of claim 14, wherein the fourth transistor includes a gate coupled to a data input from a transmission line.

### Claim 19 (depends on 14)

The semiconductor chip of claim 14, wherein the fourth transistor and the second current source are part of a first leg of the second current mirror having a second leg, wherein the first leg is coupled to a first part of a differential data signal, and wherein the second leg is coupled to a second part of the differential data signal.

### Claim 20 (depends on 14)

The semiconductor chip of claim 14, further comprising:
a first resistor coupled between the fourth transistor and the sixth transistor; and
a second resistor coupled between the second transistor and the first current source, wherein the second resistor is a replica of the first resistor.

### Claim 21 (depends on 14)

The semiconductor chip of claim 14, wherein the third transistor is a replica of the sixth transistor.

### Claim 22 (depends on 14)

The semiconductor chip of claim 14, further comprising a deserializer coupled to an output of the equalizer circuit.

### Claim 23

A data receiver in a semiconductor chip, the data receiver comprising:
means for reshaping a differential data signal, including applying a gain to the differential data signal, wherein the gain equals a transconductance of a first transistor times a resistance;
means for adjusting a current through the first transistor, including means for applying a bias voltage to a current source in the reshaping means, wherein the bias voltage applying means includes:
a second transistor and a third transistor arranged in a current mirror architecture; and
a first operational amplifier (op amp) coupled to a drain of the second transistor and to a gate of the third transistor and having a feedback loop configured to adjust the bias voltage; and
means for deserializing the differential data signal.

### Claim 24 (depends on 23)

The data receiver of claim 23, further comprising:
means for adjusting the resistance of the reshaping means.

### Claim 25 (depends on 24)

The data receiver of claim 24, wherein the resistance adjusting means comprises:
means for maintaining a common mode voltage of the reshaping means.

### Claim 26 (depends on 23)

The data receiver of claim 23, wherein the third transistor is a replica of the first transistor.

### Claim 27 (depends on 23)

The data receiver of claim 23, wherein the bias voltage applying means further includes a second op amp coupled to a drain of the third transistor and to the gate of the third transistor.