# US 2021/0175331 A1 · Semiconductor Device Having Transistors In Which Source/Drain Regions Are Shared

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- Number: US 2021/0175331 A1
- Document ID: US20210175331A1
- Status: Published application
- Kind: A1
- Application number: 17/179,198
- Filed: 2021-02-18
- Published: 2021-06-10
- Earliest claimed: 2019-07-17
- Assignees: Micron Technology, Inc.
- Applicants: Micro Technology, Inc.
- Inventors: Toshinao Ishii
- Web page: https://patentgrep.com/patent/US20210175331A1

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/412: using field-effect transistors only
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C 7/106: {Data output latches}
- G11C 7/1087: {Data input latches}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Disclosed herein is an apparatus that includes: a first diffusion region having a rectangular shape and including first and second source/drain regions arranged in the first direction; a second diffusion region having a rectangular shape and including third to fifth source/drain regions arranged in the first direction; a first gate electrode extending in a second direction, and provided between the first and second source/drain regions and between the third and fourth source/drain regions; and a second gate electrode extending in the second direction, and provided between the fourth and fifth source/drain regions. The first and third source/drain regions are brought into the same potential as each other, and the second and fourth source/drain regions are brought into the same potential as each other.

## Claims

### Claim 1

An apparatus comprising:
a first transistor in which a gate width is a first width; and
a second transistor in which a gate width is a second width smaller than the first width,
wherein source/drain regions of the first transistor is divided into first source/drain regions and second source/drain regions, and
wherein one of the first source/drain regions of the first transistor and one of source/drain regions of the second transistor are shared such that a gate width of the first transistor in the first source/drain regions is the second width.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein a gate width of the first transistor in the second source/drain regions is the second width.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising a first wiring electrically connected between the one of the first source/drain regions of the first transistor and one of the second source/drain regions of the first transistor.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein other of the first source/drain regions of the first transistor and other of the second source/drain regions of the first transistor are free from a via conductor.

### Claim 5 (depends on 4)

The apparatus of claim 4, further comprising a third transistor in which a gate width is the first width,
wherein source/drain regions of the third transistor is divided into third source/drain regions and fourth source/drain regions,
wherein the other of the first source/drain regions of the first transistor and one of the third source/drain regions of the third transistor are shared, and
wherein the other of the second source/drain regions of the first transistor and one of the fourth source/drain regions of the third transistor are shared.

### Claim 6 (depends on 5)

The apparatus of claim 5, further comprising a second wiring electrically connected between other of the third source/drain regions of the third transistor and other of the fourth source/drain regions of the first transistor.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the first and third transistors are connected in series.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein a drain of the first transistor and a drain of the second transistor have a same potential.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the first transistor comprises a first diffusion region having a rectangular shape divided into two parts and the second transistor comprises a second diffusion region having a rectangular shape, and
wherein a height of one of the divided parts of the first diffusion region of the first transistor matches a height of the second diffusion region of the second transistor.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the first transistor and the second transistor share a common drain.

### Claim 11

An apparatus comprising:
a first power supply line extending in a first direction;
a second power supply line extending in the first direction; and
a plurality of standard cells arranged in the first direction between the first power supply line and the second power supply line, wherein each of the standard cells comprises:
a first transistor including a first gate having a first gate width;
a second transistor including a second gate having a second gate width smaller than the first gate width, wherein the first and second transistors share a source/drain region as a common source, and wherein the first gate has a gate width in the shared source drain region that matches the second gate width.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein a height of the plurality of standard cells is constant, and wherein the height is measured in a second direction perpendicular to the first direction.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the first power supply line is configured to be provided with a first power potential and the second power supply line is configured to be provided with a second power potential, and wherein each of the standard cells operates on a voltage between the first power supply potential supplied and the second power supply potential.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein each of the standard cells further comprises:
a plurality of gate electrodes;
a plurality of diffusion regions having a rectangular shape overlapping with respective gate electrodes extending in a second direction perpendicular to the first direction; and
a plurality of source/drain regions not overlapping with the plurality of gate electrodes and the plurality of diffusion regions.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein a drain of the first transistor is connected to a gate electrode of the second transistor via a wiring pattern.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the first transistor and the second transistor are configured to output an output signal via the wiring pattern.

### Claim 16

An apparatus comprising:
a first transistor in which a gate width is a first width, the first transistor associated with a first gate electrode,
a second transistor in which a gate width is a second width smaller than the first width, the second transistor associated with a second electrode; and
a plurality of diffusion regions comprising first and second diffusion regions,
wherein the first gate electrode is configured to overlap with the first and second diffusion regions and the second gate electrode is configured to overlap with the second diffusion region, and
wherein a source/drain region is shared by the first and second transistors.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the source/drain region is shared with a common gate width and a differential gate width separated from the common gate width.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the common gate width corresponds to the second width and the differential gate width corresponds to a difference between the first gate width and the second gate width.

### Claim 19 (depends on 16)

The apparatus of claim 16, further comprising a third transistor in which a gate width is a third width, wherein the third width is greater than the first width and the second width, wherein the first, second, and third transistors share source/drain regions with the second width and a differential gate width corresponding to a difference between the first width and the second width.

### Claim 20 (depends on 16)

The apparatus of claim 16, wherein each diffusion region of the plurality of diffusion regions is rectangular.