# US 2021/0175136 A1 · Heterogenous Integration for RF, Microwave and MM Wave Systems in Photoactive Glass Substrates > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0175136 A1 - Document ID: US20210175136A1 - Status: Published application - Kind: A1 - Application number: 17/263,805 - Filed: 2019-12-26 - Published: 2021-06-10 - Earliest claimed: 2018-12-28 - Assignees: 3D Glass Solutions, Inc. - Applicants: 3D Glass Solutions, Inc. - Inventors: Jeb H. Flemming; Kyle McWethy - Web page: https://patentgrep.com/patent/US20210175136A1 ## CPC - H10W 70/20: Conductive package substrates serving as an interconnection, e.g. metal plates (leadframes H10W70/40) - H10W 76/138: having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type - H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 76/01: Manufacture or treatment - H10W 44/206: {Wires} - H10W 44/209: {Vertical interconnections, e.g. vias} - H10W 44/234: {Arrangements for impedance matching} - H10W 44/241: {for passive devices or passive elements} - H10W 44/248: {for antennas} - H10W 44/251: {for monolithic microwave integrated circuits [MMIC]} - H10W 46/301: {for alignment} - H10W 46/501: {for use before dicing} - H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing} - H10W 72/0198: {batch processes} - H10W 72/073: {of die-attach connectors} - H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass. ## Claims ### Claim 1 A method for creating a system in a package with integrated lumped element devices formed as a heterogeneous integration system-on-chip (HiSoC) comprising the steps of: forming a spacer by: exposing at least one portion of the photosensitive glass substrate with an activating energy source; heating the photosensitive glass substrate for at least ten minutes above its glass transition temperature; cooling the photosensitive glass substrate to transform at least a part of the exposed glass to a crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate with an etchant solution to form one or more channels or vias in the glass-crystalline substrate, wherein the glass-crystalline substrate adjacent to the trenches or vias, which may optionally be converted to a ceramic phase; depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate exposed during the etching step to enable electroplating of copper to fill the trenches on the surface or in the vias of the spacer; and connecting a high electron mobility transistor (HEMT) or other active device to a copper plate or copper ground plate via the spacer wafer; wherein the spacer reduces a parasitic noise and losses by at least 25% from a package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass when compared to an equivalent surface mounted device. ### Claim 2 (depends on 1) The method of claim 1, further comprising masking the copper plate or copper ground plate to produce a design layout comprising one or more rectangular structures with a global alignment mark and a local alignment mark within the pattern. ### Claim 3 (depends on 1) The method of claim 1, wherein the HiSoC reduces the parasitic noise and losses at least 30, 35, 40, 45, 50, or 60% when compared to an equivalent surface mounted device. ### Claim 4 (depends on 1) The method of claim 1, further comprising at least one of: forming an isolator with integrated lump element devices is in a SiP; forming a circulator with integrated lump element devices in a SiP; further comprising forming an RF filter with integrated lump element devices in a SiP; forming at least one of a low pass, high pass filter, notch filter, band pass filter, transformer, circulator, coupler, isolator, with integrated lump element devices in a SiP; forming a power combiner, a power splitter RF Circuit in or on the photo-definable glass substrate; or forming one or more RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Duplexer, or Diplexers. ### Claim 5 (canceled) ### Claim 6 (canceled) ### Claim 7 (canceled) ### Claim 8 (canceled) ### Claim 9 (depends on 1) The method of claim 1, further comprising forming a SiP RF Circuit that eliminates at least 30% or 35% of the RF parasitic signal associated with the packaging a mount elements to a substrate. ### Claim 10 (canceled) ### Claim 11 (depends on 1) The method of claim 1, wherein the device comprises one or more layers. ### Claim 12 (canceled) ### Claim 13 A package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass made by a method comprising: forming a spacer by: exposing at least one portion of the photosensitive glass substrate with an activating energy source; heating the photosensitive glass substrate for at least ten minutes above its glass transition temperature; cooling the photosensitive glass substrate to transform at least a part of the exposed glass to a crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate with an etchant solution to form one or more channels or vias in the glass-crystalline substrate, wherein the glass-crystalline substrate adjacent to the trenches or vias, which may optionally be converted to a ceramic phase; depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate exposed during the etching step to enable electroplating of copper to fill the trenches on the surface or in the vias of the spacer; and connecting a high electron mobility transistor (HEMT) or other active device to a copper plate or copper ground plate via the spacer wafer; wherein the spacer reduces a parasitic noise and losses by at least 25% from a package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass when compared to an equivalent surface mounted device. ### Claim 14 (depends on 13) The device of claim 13, wherein the device is at least one of an isolator with integrated lump element devices and is in a SiP; a circulator with integrated lump element devices and is in a SiP; an RF filter with integrated lump element devices and is in a SiP; at least one of a low pass, high pass filter, notch filter, band pass filter, transformer, circulator, coupler, isolator, with integrated lump element devices and is in a SiP; a power combiner, a power splitter RF Circuit in or on the photo-definable glass substrate; a SiP RF Circuit that eliminates at least 15% of the RF parasitic signal associated with the packaging a mount elements to a substrate; a SiP RF Circuit that eliminates at least 25% of the RF parasitic signal associated with the packaging a mount elements to a substrate; or one or more RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Duplexers, or Diplexers. ### Claim 15 (canceled) ### Claim 16 (canceled) ### Claim 17 (canceled) ### Claim 18 (canceled) ### Claim 19 (canceled) ### Claim 20 (canceled) ### Claim 21 (canceled) ### Claim 22 A method for creating a system in a package with integrated lumped element devices formed as a system-in-package (SiP) in or on photo-definable glass comprising the steps of: masking a design layout comprising one or more structures to form one or more electrical components on or in a photosensitive glass substrate spacer; transforming at least a part of the exposed glass to a crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate with an etchant solution to form one or more channels or vias in the glass-crystalline substrate, which may optionally be converted to a ceramic phase; depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate exposed during the etching step to enable electroplating of copper to fill the vias and deposit on the surface of the photodefinable glass; and placing and electrically connecting a high electron mobility transistor (HEMT) or other active device on the copper plate or copper-coated glass wafer across the photosensitive glass substrate spacer; wherein the integrated lumped element devices reduces the parasitic noise and losses by at least 25% from a package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass when compared to an equivalent surface mounted device. ### Claim 23 (depends on 22) The method of claim 22, wherein the SiP is a heterogeneous integration system-on-chip HiSoC that reduces the parasitic noise and losses at least 30, 35, 40, 45, 50, or 60% when compared to an equivalent surface mounted device. ### Claim 24 (depends on 22) The method of claim 22, further comprising forming at least one of: an isolator with integrated lump element devices is in a SiP; a circulator with integrated lump element devices in a SiP; an RF filter with integrated lump element devices in a SiP; at least one of a low pass, high pass filter, notch filter, band pass filter, transformer, circulator, coupler, isolator, with integrated lump element devices in a SiP; a power combiner, a power splitter RF Circuit in or on the photo-definable glass substrate. ### Claim 25 (canceled) ### Claim 26 (canceled) ### Claim 27 (canceled) ### Claim 28 (canceled) ### Claim 29 (depends on 22) The method of claim 22, further comprising forming an SiP RF Circuit that eliminates at least 25, 30 or 30% of the RF parasitic signal associated with the packaging a mount elements to a substrate. ### Claim 30 (canceled) ### Claim 31 (canceled) ### Claim 32 (depends on 22) The method of claim 22, further comprising forming one or more RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Duplexers, and/or Diplexers. ### Claim 33 A method for creating a system in a package with integrated lumped element devices formed as a heterogeneous integration system-on-chip (HiSoC) using photo-definable glass comprising the steps of: forming an integrated passive device (IPD) wafer by: obtaining a copper plate/substrate coating the copper plate/substrate with a photoresist in an alignment pattern for one or more dies; using the alignment marks to pick, place and bond an active device to the copper plate/substrate; depositing solder bonding balls on one or more contact pads of the active device; forming a spacer wafer by: lap and polish a spacer wafer of photodefinable glass; exposing, baking and etching one or more through hole openings or through hole vias to provide an electrical connection through the spacer wafer; depositing a seed layer of Ti/Cu by chemical vapor deposition (CVD) on the spacer wafer; electroplating or electroless plating copper into the through hole openings or the through hole vias in the spacer wafer; removing excess cooper to reduce a thickness of the copper on the spacer wafer; coating, exposing and developing a photoresist in a pattern on a first side of the spacer wafer, wherein the pattern has a spacer edge area that is smaller than the pattern on the spacer wafer; coating the first side of the spacer wafer with an electrically conductive material with a sputter deposition system; removing the photoresist to leave the electrically conductive material in a continuous pattern; uniformly coating a second side of the spacer wafer with an electrically conductive material using a sputter deposition system; aligning the spacer wafer on the copper substrate with the alignment marks; bonding the spacer and to the copper substrate; depositing solder ball on an opposite side of the spacer wafer at the one or more through hole opening or through hole vias; and using the alignment marks to electrically connect the integrated passive device (IPD) wafer to the spacer wafer with solder balls to connect to the active device to a ground.