# US 2021/0174884 A1 · Methods of programming memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0174884 A1
- Document ID: US20210174884A1
- Status: Published application
- Kind: A1
- Application number: 17/179,356
- Filed: 2021-02-18
- Published: 2021-06-10
- Earliest claimed: 2019-10-31
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Jianquan Jia; Kaikai You; Ying Cui; Kaiwei Li; Yali Song; Shan Li; An Zhang
- Web page: https://patentgrep.com/patent/US20210174884A1

## CPC

- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.

## Claims

### Claim 1

A memory device, comprising:
a memory array comprising memory strings, each memory string comprising a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells;
a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells;
one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells; and
a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines, wherein, to program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the biased dummy word line pre-pulse signal is a negative voltage signal.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein
the control circuit is configured to program in a direction from the bottom memory cells to the top memory cells; and
the target memory cell is one of the top memory cells.

### Claim 4 (depends on 1)

The memory device of claim 1, further comprising a bit line coupled to a drain terminal of an unselected memory string of the memory strings, wherein, to program the target memory cell, the control circuit is further configured to apply a biased bit line pre-pulse signal to the bit line in the pre-charge period.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the target memory cell is in a selected memory string of the memory strings different from the unselected memory string.

### Claim 6 (depends on 4)

The memory device of claim 4, wherein the biased bit line pre-pulse signal is a positive voltage signal.

### Claim 7 (depends on 4)

The memory device of claim 4, wherein, to program the target memory cell, the control circuit is further configured to:
apply a selected word line signal to the selected word line in the pre-charge period; and
apply an unselected word line signal to unselected word lines of the plurality of word lines in the pre-charge period.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein the selected word line signal and the unselected word line signal each is a ground voltage.

### Claim 9 (depends on 4)

The memory device of claim 4, wherein
the unselected memory string further comprises a top select gate (TSG) transistor between the bit line and the top memory cells; and
to program the target memory cell, the control circuit is further configured to apply a biased TSG pre-pulse signal to the TSG transistor in the pre-charge period.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the biased TSG pre-pulse signal is a positive voltage signal.

### Claim 11

A method for programming a memory device, the memory device comprising memory strings, each memory string comprising a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells, the method comprising:
programming a target memory cell coupled to a selected word line of a plurality of word lines, the plurality of word lines being respectively coupled to gate terminals of the top memory cells and the bottom memory cells,
wherein programming the target memory cell comprises applying a biased dummy word line pre-pulse signal to one or more dummy word lines in a pre-charge period prior to a programming period, the one or more dummy word lines being respectively coupled to gate terminals of the one or more dummy memory cells.

### Claim 12 (depends on 11)

The method of claim 11, wherein the biased dummy word line pre-pulse signal is a negative voltage signal.

### Claim 13 (depends on 11)

The method of claim 11, wherein
the memory device is programmed in a direction from the bottom memory cells to the top memory cells; and
the target memory cell is one of the top memory cells.

### Claim 14 (depends on 11)

The method of claim 11, wherein
the memory device further comprises a bit line coupled to a drain terminal of an unselected memory string of the memory strings; and
programming the target memory cell further comprises applying a biased bit line pre-pulse signal to the bit line in the pre-charge period.

### Claim 15 (depends on 14)

The method of claim 14, wherein the target memory cell is in a selected memory string of the memory strings different from the unselected memory string.

### Claim 16 (depends on 14)

The method of claim 14, wherein the biased bit line pre-pulse signal is a positive voltage signal.

### Claim 17 (depends on 14)

The method of claim 14, wherein programming the target memory cell further comprises:
applying a selected word line signal to the selected word line in the pre-charge period; and
applying an unselected word line signal to unselected word lines of the plurality of word lines in the pre-charge period.

### Claim 18 (depends on 17)

The method of claim 17, wherein the selected word line signal and the unselected word line signal each is a ground voltage.

### Claim 19 (depends on 14)

The method of claim 14, wherein
the unselected memory string further comprises a top select gate (TSG) transistor between the bit line and the top memory cells; and
programming the target memory cell further comprises applying a biased TSG pre-pulse signal to the TSG transistor in the pre-charge period.

### Claim 20 (depends on 19)

The method of claim 19, wherein the biased TSG pre-pulse signal is a positive voltage signal.