# US 2021/0174875 A1 · Fractional program commands for memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0174875 A1 - Document ID: US20210174875A1 - Status: Published application - Kind: A1 - Application number: 16/953,182 - Filed: 2020-11-19 - Published: 2021-06-10 - Earliest claimed: 2008-05-13 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Brent S. Haukness; Ian Shaeffer; Gary Bela Bronner - Web page: https://patentgrep.com/patent/US20210174875A1 ## CPC - G11C 16/10: Programming or data input circuits - G06F 3/0611: {in relation to response time} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F 2212/7204: Capacity control, e.g. partitioning, end-of-life degradation - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells. ## Claims ### Claim 1 (canceled) ### Claim 2 A Flash memory device, comprising: Flash memory cells; a circuit to receive fractional program commands, the circuit receiving an address specifying a group of the Flash memory cells for a program operation in accordance with the fractional program commands, the circuit responsive to a first one of the fractional program commands to apply a first fractional program pulse to program first data in the group of the Flash memory cells; verify whether the first fractional program pulse completely programmed the first data in the group of Flash memory cells; generate verification data indicating a result of the verify; and wherein the circuit is responsive to a subsequent fractional program command to selectively apply a second fractional program pulse to program the first data in the group of Flash memory cells based on the verification data. ### Claim 3 (depends on 2) The Flash memory device of claim 2, wherein the fractional program commands each comprise an independently executable command. ### Claim 4 (depends on 3) The Flash memory device of claim 3, wherein the fractional program commands are derived from a single program command to carry out the program operation. ### Claim 5 (depends on 3) The Flash memory device of claim 3, wherein the fractional program commands are received from a Flash memory controller. ### Claim 6 (depends on 5) The Flash memory device of claim 5, wherein the circuit includes transmit circuitry to transfer the verification data to the Flash memory controller. ### Claim 7 (depends on 2) The Flash memory device of claim 2, wherein the program operation terminates based on the verification data. ### Claim 8 (depends on 2) The Flash memory device of claim 2, further comprising: a control circuit to receive a program command, corresponding to the program operation, the control circuit to generate the fractional program commands in response to receiving the program command, and to transfer the fractional program commands to the circuit. ### Claim 9 A method of operation in a Flash memory device, the method comprising: receiving, via a circuit, fractional program commands and an address specifying a group of Flash memory cells for a program operation in accordance with the fractional program commands; executing a first one of the fractional program commands by applying a first fractional program pulse to program first data in the group of the Flash memory cells; verifying whether the first fractional program pulse completely programmed the first data in the group of Flash memory cells; generating verification data indicating a result of the verifying; and executing a subsequent fractional program command to selectively apply a second fractional program pulse to program the first data in the group of Flash memory cells based on the verification data. ### Claim 10 (depends on 9) The method of claim 9, wherein executing comprises independently executing each fractional program command. ### Claim 11 (depends on 9) The method of claim 9, further comprising: transferring the verification data to a Flash memory controller. ### Claim 12 (depends on 9) The method of claim 9, further comprising: terminating the program operation based on the verification data. ### Claim 13 (depends on 9) The method of claim 9, further comprising: receiving a program command, corresponding to the program operation; deriving the fractional program commands on-chip in response to receiving the program command; and transferring the fractional program commands to the circuit. ### Claim 14 (depends on 9) The method of claim 9, wherein executing comprises executing each fractional program command in accordance with a command protocol. ### Claim 15 A device, comprising: a circuit to execute fractional program commands for a program operation directed to an addressed group of Flash memory cells, the circuit responsive to a first one of the fractional program commands to apply a first fractional program pulse to program first data in the addressed group of Flash memory cells; verify whether the first fractional program pulse completely programmed the first data in the addressed group of Flash memory cells; generate verification data indicating a result of the verify; and wherein the circuit is responsive to a subsequent fractional program command to selectively apply a second fractional program pulse to program the first data based on the verification data. ### Claim 16 (depends on 15) The device of claim 15, wherein the fractional program commands each comprise an independently executable command. ### Claim 17 (depends on 16) The device of claim 16, wherein the fractional program commands are incorporated into a command protocol for operating the Flash memory. ### Claim 18 (depends on 17) The device of claim 17, wherein the fractional program commands are received from a Flash memory controller. ### Claim 19 (depends on 15) The device of claim 15, wherein the circuit includes transmit circuitry to transfer the verification data to a Flash memory controller. ### Claim 20 (depends on 15) The device of claim 15, wherein the program operation terminates based on the verification data. ### Claim 21 (depends on 15) The device of claim 15, further comprising: a control circuit to receive a program command, corresponding to the program operation, the control circuit to generate the fractional program commands in response to receiving the program command, and transfer the fractional program commands to the circuit.