# US 2021/0173786 A1 · Storage System and Method for Caching a Single Mapping Entry for a Random Read Command > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0173786 A1 - Document ID: US20210173786A1 - Status: Published application - Kind: A1 - Application number: 16/708,054 - Filed: 2019-12-09 - Published: 2021-06-10 - Earliest claimed: 2019-12-09 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Ramanathan Muthiah; Kshitij Gupta - Web page: https://patentgrep.com/patent/US20210173786A1 ## CPC - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 12/1009: using page tables, e.g. page table structures - G06F 2212/1044: Space efficiency improvement - G06F 2212/608: Details relating to cache mapping - G06F 2212/65: Details of virtual memory and virtual address translation - G06F 2212/684: TLB miss handling - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A storage system and method for caching a single mapping entry for a random read command are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to determine whether a read command received from a host is a random read command, wherein the read command comprises a logical address; and in response to determining that the read command received from the host is a random read command, caching only an associated logical-to-physical address map entry from a logical-to-physical address map stored in the memory instead of caching a larger segment of the logical-to-physical address map that contains the entry and other entries. Other embodiments are provided. ## Claims ### Claim 1 A method for caching a single mapping entry for a random read command, the method comprising: performing the following in a storage system in communication with a host, wherein the storage system comprises a memory storing a logical-to-physical address translation data structure: receiving a read command from the host, wherein the read command comprises a logical address; determining that the host is operating in random read mode; and in response to determining that the host is operating in random read mode, caching only an entry from the logical-to-physical address translation data structure that corresponds to the logical address of the read command, wherein entries of the logical-to-physical address translation data structure that correspond other logical addresses are not cached. ### Claim 2 (depends on 1) The method of claim 1, wherein the storage system determines that the host is operating in random read mode by receiving an indication from the host. ### Claim 3 (depends on 1) The method of claim 1, wherein the storage system determines that the host is operating in random read mode by analyzing a plurality of previously-received read commands from the host. ### Claim 4 (depends on 1) The method of claim 1, further comprising, prior to caching the entry: determining an offset of the entry in a page of the logical-to-physical address translation data structure that contains additional entries for other logical addresses; and performing a latch transfer and error correction decoding on a subpage containing the entry. ### Claim 5 (depends on 1) The method of claim 1, further comprising: using the cached entry to perform logical-to-physical address translation of the logical address of the read command; and deleting the cached entry after the translation is performed. ### Claim 6 (depends on 5) The method of claim 5, further comprising receiving another read command from the host with the logical address; and re-caching the entry from the logical-to-physical address translation data structure that corresponds to the logical address. ### Claim 7 (depends on 1) The method of claim 1, further comprising receiving a write command for the logical address; and in response to receiving the write command for the logical address, instead of using the cached entry, caching a page of the logical-to-physical address translation data structure that contains the entry and additional entries for other logical addresses. ### Claim 8 A storage system comprising: a memory; and a controller configured to be in communication with the memory, wherein the controller is further configured to: determine whether a read command received from a host is a random read command, wherein the read command comprises a logical address; and in response to determining that the read command received from the host is a random read command, caching only a logical-to-physical address map entry associated with the logical address from a logical-to-physical address map stored in the memory instead of caching a larger segment of the logical-to-physical address map that contains the entry and other entries. ### Claim 9 (depends on 8) The storage system of claim 8, wherein the controller is further configured to perform at least one of the following to determine whether the read command received from the host is a random read command: receive a directive from the host that the read command received from the host is a random read command; and analyze a plurality of previously-received read commands from the host to detect a pattern, which indicates that the read command received from the host is a random read command. ### Claim 10 (depends on 9) The storage system of claim 9, wherein the controller is configured to both receive the directive and analyze the plurality of previously-received read commands. ### Claim 11 (depends on 8) The storage system of claim 8, wherein the controller is further configured to: determine an offset of the entry in the logical-to-physical address map; and perform a latch transfer and error correction decoding on a subpage containing the entry. ### Claim 12 (depends on 8) The storage system of claim 8, wherein the controller is further configured to: use the cached entry to perform logical-to-physical address translation of the logical address of the read command; and delete the cached entry after the translation is performed. ### Claim 13 (depends on 12) The storage system of claim 12, wherein the controller is further configured to: receive another read command from the host with the logical address; and re-cache the entry from the logical-to-physical address map that corresponds to the logical address. ### Claim 14 (depends on 8) The storage system of claim 8, wherein the controller is further configured to: receive a write command for the logical address; and in response to receiving the write command for the logical address, instead of using the cached entry, cache a larger segment of the logical-to-physical address map that contains the entry. ### Claim 15 (depends on 8) The storage system of claim 8, wherein the memory comprises a three-dimensional memory. ### Claim 16 (depends on 8) The storage system of claim 8, wherein the storage system is configured to be integrated in the host. ### Claim 17 (depends on 8) The storage system of claim 8, wherein the storage system is configured to be removably connected with the host. ### Claim 18 A storage system comprising: a memory; means for determining whether a read command received from a host is a random read command, wherein the read command comprises a logical address; and means for, in response to determining that the read command is a random read command, using a caching mode in which only a logical-to-physical address mapping entry for the logical address is cached. ### Claim 19 (depends on 18) The storage system of claim 18, wherein the means for determining whether the read command is a random read command comprises one or both of the following: means for receiving an instruction from the host that the read command is a random read command; and means for analyzing a plurality of previously-received read commands from the host to detect a pattern, which indicates that the read command received from the host is a random read command. ### Claim 20 (depends on 18) The storage system of claim 18, further comprising: means for determining an offset of the logical-to-physical address mapping entry in a logical-to-physical address map; and means for performing a latch transfer and error correction decoding on a subpage containing the logical-to-physical address mapping entry.