# US 2021/0173669 A1 · Fast boot systems and methods for programmable logic devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0173669 A1 - Document ID: US20210173669A1 - Status: Published application - Kind: A1 - Application number: 16/706,591 - Filed: 2019-12-06 - Published: 2021-06-10 - Earliest claimed: 2019-12-06 - Assignees: Lattice Semiconductor Corporation - Applicants: Lattice Semiconductor Corporation - Inventors: Fulong Zhang; Gordon HANDS; Wei HAN; Mark EVERHARD - Web page: https://patentgrep.com/patent/US20210173669A1 ## CPC - G06F 1/24: Resetting means - G06F 9/44505: {Configuring for program initiating, e.g. using registry, configuration files} - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57) - G06F 9/4406: {Loading of operating system} - G06F 9/4411: {Configuring for operating with peripheral devices; Loading of device drivers} - G06F 15/7871: {Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided. ## Claims ### Claim 1 A method comprising: performing a first read operation on a non-volatile memory to obtain a first value; comparing the first value to a first predetermined value to obtain a first comparison result; determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result; performing, based on the determining, a second read operation on the boot image to obtain data associated with booting of a device; and booting the device based at least on the data. ### Claim 2 (depends on 1) The method of claim 1, wherein the first predetermined value comprises a value associated with the serial flash discoverable parameters (SFDP) standard. ### Claim 3 (depends on 1) The method of claim 1, wherein the first predetermined value is stored at a predetermined address of the non-volatile memory. ### Claim 4 (depends on 1) The method of claim 1, further comprising initiating power on of the device, wherein the first read operation is performed by the device immediately after power on of the device is complete. ### Claim 5 (depends on 1) The method of claim 1, further comprising: performing a third read operation on the non-volatile memory to obtain a second value; and comparing the second value to the first predetermined value to obtain a second comparison result, wherein the determining whether the boot image is to be read is further based on the second comparison result. ### Claim 6 (depends on 5) The method of claim 5, wherein the first read operation and the third read operation are consecutive read operations on the same portion of the non-volatile memory. ### Claim 7 (depends on 1) The method of claim 1, wherein the boot image is determined to be to be read when a value obtained from each of at least a number of consecutive read operations on the non-volatile memory matches the first predetermined value. ### Claim 8 (depends on 1) The method of claim 1, wherein the first read operation is performed on a first portion of the non-volatile memory, the method further comprising: performing a third read operation on a second portion of the non-volatile memory to obtain a second value, wherein the second portion is different from the first portion; and comparing the second value to a second predetermined value to obtain a second comparison result, wherein the determining is further based on the second comparison result. ### Claim 9 (depends on 8) The method of claim 8, wherein the first read operation and the third read operation are consecutive read operations on the non-volatile memory. ### Claim 10 (depends on 1) The method of claim 1, wherein: the device is a programmable logic device (PLD); the data comprises configuration data; the booting comprises: programming at least a portion of the PLD with the configuration data; and providing at least one wakeup signal to wake up functionality associated with the PLD. ### Claim 11 (depends on 9) The method of claim 9, wherein the programming comprises: programming a first portion of the PLD with a first portion of the configuration data; programming a second portion of the PLD with a second portion of the configuration data; providing a first wakeup signal to wake up functionality associated with the first portion of the PLD; and providing a second wakeup signal to wake up functionality associated with the second portion of the PLD. ### Claim 12 A programmable logic device (PLD) comprising: an array of configuration memory cells; a processing circuit configured to: perform a first read operation on a non-volatile memory to obtain a first value; compare the first value to a first predetermined value to obtain a first comparison result; determine whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result; perform, based on determining whether the boot image is to be read, a second read operation on the boot image to obtain data associated with booting of the PLD; and boot the PLD based at least on the data. ### Claim 13 (depends on 12) The PLD of claim 12, wherein the first predetermined value comprises a value associated with the serial flash discoverable parameters (SFDP) standard and/or stored at a predetermined address of the non-volatile memory, wherein the processing circuit is further configured to initiate power on of the PLD, and wherein the processing circuit is configured to perform the first read operation immediately after power on of the PLD is complete. ### Claim 14 (depends on 12) The PLD of claim 12, wherein the processing circuit is further configured to: perform a third read operation on the non-volatile memory to obtain a second value; and compare the second value to the first predetermined value to obtain a second comparison result, wherein the determining whether the boot image is to be read is further based on the second comparison result. ### Claim 15 (depends on 14) The PLD of claim 14, wherein the first read operation and the third read operation are consecutive read operations on the same portion of the non-volatile memory. ### Claim 16 (depends on 12) The PLD of claim 12, wherein the boot image is determined to be to be read when a value obtained from each of at least a number of consecutive read operations on the non-volatile memory matches the first predetermined value. ### Claim 17 (depends on 12) The PLD of claim 12, wherein the first read operation is performed on a first portion of the non-volatile memory, wherein the processing circuit is further configured to: perform a third read operation on a second portion of the non-volatile memory to obtain a second value, wherein the second portion is different from the first portion; and compare the second value to a second predetermined value to obtain a second comparison result, wherein the processing circuit is configured to determine whether the boot image is to be read based further on the second comparison result. ### Claim 18 (depends on 17) The PLD of claim 17, wherein the first read operation and the third read operation are consecutive read operations on the non-volatile memory. ### Claim 19 (depends on 12) The PLD of claim 12, wherein: the data comprises configuration data; the processing circuit is configured to boot the PLD by: programming at least a subset of the configuration memory cells with the configuration data; and providing at least one wakeup signal to wake up functionality associated with the PLD. ### Claim 20 (depends on 19) The PLD of claim 19, wherein the programming comprises: programming a first subset of the configuration memory cells with a first portion of the configuration data; programming a second subset of the configuration memory cells with a second portion of the configuration data; providing a first wakeup signal to wake up functionality associated with the first subset of the configuration memory cells; and providing a second wakeup signal to wake up functionality associated with the second subset of the configuration memory cells.