# US 2021/0173659 A1 · Neural network processor, chip and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0173659 A1 - Document ID: US20210173659A1 - Status: Published application - Kind: A1 - Application number: 17/113,016 - Filed: 2020-12-05 - Published: 2021-06-10 - Earliest claimed: 2019-12-09 - Assignees: Guangdong Oppo Mobile Telecommunications Corp., Ltd. - Applicants: Guangdong Oppo Mobile Telecommunications Corp., Ltd. - Inventors: Shengguang YUAN - Web page: https://patentgrep.com/patent/US20210173659A1 ## CPC - G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3889: {controlled by multiple instructions, e.g. MIMD, decoupled access or execute} - G06F 12/0207: {with multidimensional access, e.g. row/column, matrix} - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G06F 13/1668: {Details of memory controller} - G06F 15/78: comprising a single central processing unit - G06F 17/153: {Multidimensional correlation or convolution} - G06N 3/045: Combinations of networks - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/063: using electronic means - G06N 3/08: Learning methods - G06F 2212/1016: Performance improvement - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract The embodiments of the disclosure provide a neural network processor, a chip and an electronic device. The neural network processor includes a convolution processing unit, a vector processing unit, and an instruction issue module. The convolution processing unit and the vector processing unit are both connected to the instruction issue module. The instruction issue module is configured to issue a plurality of instructions to the convolution processing unit and the vector processing unit in parallel. The embodiments of the application can improve the efficiency of the neural network processor processing data. ## Claims ### Claim 1 A neural network processor, comprising: a convolution processing unit; a vector processing unit; and an instruction issue module, wherein the convolution processing unit and the vector processing unit are both in communication with the instruction issue module, and the instruction issue module is configured to issue a plurality of instructions to the convolution processing unit and the vector processing unit in parallel. ### Claim 2 (depends on 1) The neural network processor according to claim 1, wherein the instruction issue module is configured to issue the plurality of instructions to the convolution processing unit and the vector processing unit in parallel within one clock cycle. ### Claim 3 (depends on 1) The neural network processor according to claim 1, wherein the instruction issue module is configured to issue the plurality of instructions to the convolution processing unit and the vector processing unit in parallel, according to types of the plurality of instructions. ### Claim 4 (depends on 1) The neural network processor according to claim 1, further comprising a scalar processing unit in communication with the instruction issue module, wherein the instruction issue module is further configured to issue the plurality of instructions to the convolution processing unit and the scalar processing unit in parallel within one clock cycle. ### Claim 5 (depends on 1) The neural network processor according to claim 1, further comprising a scalar processing unit in communication with the instruction issue module, wherein the instruction issue module is further configured to issue the plurality of instructions to the convolution processing unit and the scalar processing unit in parallel, according to types of the plurality of instructions. ### Claim 6 (depends on 1) The neural network processor according to claim 1, further comprising a scalar processing unit in communication with the instruction issue module, wherein the instruction issue module is further configured to issue the plurality of instructions to the convolution processing unit, the vector processing unit and the scalar processing unit in parallel. ### Claim 7 (depends on 6) The neural network processor according to claim 6, further comprising a shaping processing unit in communication with the instruction issue module, wherein the instruction issue module is configured to issue the plurality of instructions to the convolution processing unit, the vector processing unit, the scalar processing unit and the shaping processing unit in parallel. ### Claim 8 (depends on 1) The neural network processor according to claim 1, wherein the plurality of instructions issued by the instruction issue module comprises a fine-grained instruction, the instruction issue module is configured to issue the fine-grained instruction to the convolution processing unit, and the convolution processing unit is configured to perform, according to the fine-grained instruction, a dot product operation on its' received data. ### Claim 9 (depends on 1) The neural network processor according to claim 1, further comprising a data storage module configured for data storage, the data storage module is in communication with both of the convolution processing unit and the vector processing unit. ### Claim 10 (depends on 9) The neural network processor according to claim 9, wherein the data storage module is further in communication with the instruction issue module; the instruction issue module is further configured to: issue the plurality of instructions to the convolution processing unit and the vector processing unit in parallel, in response to that the data storage module has data to-be-processed stored therein; do not issue any instruction to the convolution processing unit and the vector processing unit, in response to that the data storage module does not store the data to-be-processed therein. ### Claim 11 (depends on 9) The neural network processor according to claim 9, further comprising a scalar processing unit in communication with the instruction issue module, wherein the data storage module is further in communication with both of the scalar processing unit and the instruction issue module; the instruction issue module is further configured to: issue the plurality of instructions to the convolution processing unit, the vector processing unit and the scalar processing unit in parallel, in response to that the data storage module has data to-be-processed stored therein; do not issue any instruction to the convolution processing unit, the vector processing unit and the scalar processing unit, in response to that the data storage module does not store the data to-be-processed therein. ### Claim 12 (depends on 9) The neural network processor according to claim 9, wherein the data storage module stores data to-be-processed therein; the convolution processing unit and the vector processing unit process the data to-be-processed to obtain one or more processing results and stores the one or more processing results into the data storage module. ### Claim 13 (depends on 12) The neural network processor according to claim 12, wherein the convolution processing unit and the vector processing unit process the data to-be-processed to obtain one or more processing results and stores the one or more processing results into the data storage module comprises: the convolution processing unit performs a first processing on the data to-be-processed to obtain an intermediate processing result and directly transmits the intermediate processing result to the vector processing unit, the vector processing unit performs a second processing on the intermediate processing result to obtain the processing result and store the processing result into the data storage module. ### Claim 14 (depends on 12) The neural network processor according to claim 12, wherein the convolution processing unit and the vector processing unit process the data to-be-processed to obtain one or more processing results and stores the one or more processing results into the data storage module comprises: the convolution processing unit performs a first processing on the data to-be-processed to obtain an intermediate processing result and stores the intermediate processing result into the data storage module, the vector processing unit acquires the intermediate processing result from the data storage module, performs a second processing on the intermediate processing result to obtain the processing result, and stores the processing result into the data storage module. ### Claim 15 (depends on 9) The neural network processor according to claim 9, further comprising an instruction storage module in communication with the instruction issue module, wherein the instruction storage module is configured to store part or all instructions required to be issued by the instruction issue module. ### Claim 16 (depends on 15) The neural network processor according to claim 15, further comprising: a system bus interface, configured to be in communication with a system bus; a data migration module, connected between the data storage module and the system bus interface, wherein the data migration module is configured to move data; and an instruction migration module, connected between the instruction storage module and the system bus interface, wherein the instruction migration module is configured to move instructions. ### Claim 17 (depends on 15) The neural network processor according to claim 15, further comprising: a system bus interface, configured to be in communication with a system bus, the system bus interface being in communication with the instruction storage module; and a data migration module, connected between the data storage module and the system bus interface, the data migration module being configured to move data. ### Claim 18 (depends on 15) The neural network processor according to claim 15, further comprising: a system bus interface, configured to be in communication with a system bus; an instruction storage module, configured to store one or more instructions, the instruction storage module being in communication with the instruction issue module; and a direct memory access, comprising at least one physical channel, at least one logical channel, and a first arbitration unit, wherein the at least one physical channel and at least one logical channel are in communication with the system bus interface through the first arbitration unit, the at least one physical channel is connected with the instruction storage module, and the at least one logical channel is connected with the data storage module. ### Claim 19 A chip, comprising: a system bus; an external memory; a central processing unit; and a neural network processor, connected to both of the external memory and the central processing unit via the system bus, wherein the neural network processor is controlled by the central processing unit to acquire data to-be-processed from the external memory, process the data to-be-processed to form a processing result, and feed back the processing result to the external memory; wherein the neural network processor comprises: a convolution processing unit; a vector processing unit; and an instruction issue module, being in communication with the instruction issue module, the instruction issue module being configured to issue a plurality of instructions to the convolution processing unit and the vector processing unit in parallel. ### Claim 20 An electronic device, comprising: a system bus; an external memory; a central processing unit; and a neural network processor, connected to both of the external memory and the central processing unit via the system bus, wherein the neural network processor is controlled by the central processing unit to acquire data to-be-processed from the external memory, process the data to-be-processed to form a processing result, and feed back the processing result to the external memory; wherein the neural network processor comprises: a convolution processing unit; a vector processing unit; and an instruction issue module, being in communication with the instruction issue module, the instruction issue module being configured to issue a plurality of instructions to the convolution processing unit and the vector processing unit in parallel.